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    Preparation Method of Low Temperature Sintering Active Electrode Paste for Dye Sensitized Solar Cell
    1.
    发明申请
    Preparation Method of Low Temperature Sintering Active Electrode Paste for Dye Sensitized Solar Cell 有权
    用于染料敏化太阳能电池的低温烧结活性电极浆料的制备方法

    公开(公告)号：US20130333757A1

    公开(公告)日：2013-12-19

    申请号：US13788912

    申请日：2013-03-07

    Applicant: Tae Jin Hwang ,  Ho Hyeong Kim ,  Jae Young Park

    Inventor： Tae Jin Hwang ,  Ho Hyeong Kim ,  Jae Young Park

    IPC: H01G9/20

    CPC classification number: H01G9/2031 ,  B82Y30/00 ,  C09C1/0084 ,  H01G9/2059 ,  Y02E10/542

    Abstract: The present invention relates to a method for preparing titanium dioxide paste for dye sensitized solar cell, and more specifically a method for preparing titanium dioxide paste fir dye sensitized solar cell, which is curable at a low temperature and is able to form a uniform coating layer and exhibits relatively high energy conversion efficiency. The present invention also relates to a method for preparing low temperature curable paste which requires no separate dye adsorption process or can improve energy conversion efficiency by adding dye or metal precursor in advance.

    Abstract translation: 本发明涉及一种制备用于染料敏化太阳能电池的二氧化钛糊料的方法，更具体地说，一种制备二氧化钛糊冷杉染料敏化太阳能电池的方法，其可在低温下固化并且能够形成均匀的涂层 并表现出较高的能量转换效率。 本发明还涉及一种制备低温可固化糊剂的方法，其不需要单独的染料吸附方法，或者可以通过预先加入染料或金属前体来提高能量转换效率。

    Input buffer circuit of semiconductor apparatus
    2.
    发明授权
    Input buffer circuit of semiconductor apparatus 有权
    半导体装置的输入缓冲电路

    公开(公告)号：US08339159B2

    公开(公告)日：2012-12-25

    申请号：US12540496

    申请日：2009-08-13

    Applicant: Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

    Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

    IPC: H03K5/153

    CPC classification number: H03K5/153

    Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

    Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

    Voltage regulator for a synchronous clock system to reduce clock tree jitter
    3.
    发明授权
    Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
    用于同步时钟系统的电压调节器，以减少时钟树抖动

    公开(公告)号：US08026701B2

    公开(公告)日：2011-09-27

    申请号：US12265908

    申请日：2008-11-06

    Applicant: Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    Inventor： Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC: G05F1/652

    CPC classification number: G11C5/147

    Abstract: A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

    Abstract translation: 具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。 第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。 电压产生单元基于参考电压产生调节电压。 微调电容器单元控制电压产生单元的负载电容。 第二缓冲链使用调节电压作为电源电压来延迟时钟信号。 控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

    DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    6.
    发明申请
    DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器的数据对准电路

    公开(公告)号：US20100309732A1

    公开(公告)日：2010-12-09

    申请号：US12647174

    申请日：2009-12-24

    Applicant: Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    Inventor： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    IPC: G11C7/10 ,  G11C7/00 ,  G11C8/00

    CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1087

    Abstract: A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.

    Abstract translation: 用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。 第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。 第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。 第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。 第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

    Duty cycle correction circuit with reduced current consumption
    10.
    发明授权
    Duty cycle correction circuit with reduced current consumption 失效
    占空比校正电路，降低电流消耗

    公开(公告)号：US07786783B2

    公开(公告)日：2010-08-31

    申请号：US12333193

    申请日：2008-12-11

    Applicant: Hee-Woong Song ,  Yong-Ju Kim ,  Sung-Woo Han ,  Jae-Min Jang ,  Hyung-Soo Kim ,  Ji-Wang Lee ,  Chang-Kun Park ,  Ic-Su Oh ,  Hae-Rang Choi ,  Tae-Jin Hwang

    Inventor： Hee-Woong Song ,  Yong-Ju Kim ,  Sung-Woo Han ,  Jae-Min Jang ,  Hyung-Soo Kim ,  Ji-Wang Lee ,  Chang-Kun Park ,  Ic-Su Oh ,  Hae-Rang Choi ,  Tae-Jin Hwang

    IPC: H03K3/017

    CPC classification number: H03K5/1565

    Abstract: A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

    Abstract translation: 一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到 所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平 输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

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