公开(公告)号：US10181476B2

公开(公告)日：2019-01-15

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US20170271463A1

公开(公告)日：2017-09-21

申请号：US15591736

申请日：2017-05-10

申请人： Tae-Wan LIM ,  Hojong KANG ,  Joowon PARK

发明人： Tae-Wan LIM ,  Hojong KANG ,  Joowon PARK

IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L23/31 ,  H01L27/11582 ,  H01L21/28 ,  H01L23/485 ,  H01L23/522 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11575 ,  H01L21/768

CPC分类号： H01L29/4234 ,  H01L21/28282 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

公开(公告)号：US20160204111A1

公开(公告)日：2016-07-14

申请号：US14965532

申请日：2015-12-10

申请人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-Yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

摘要翻译： 垂直存储器件及其制造方法包括提供包括电池阵列区域和外围电路区域的衬底，在电池阵列区域中形成模具结构，形成通过模具结构的共同源极线的开口，以及 在垂直于衬底的顶表面的第一方向上延伸，形成第一接触插塞，该第一接触插塞具有限定用于公共源极线的开口中的凹陷区域的内侧壁，以及形成与内侧壁电连接的公共源位线接触 的第一个接触插头。

公开(公告)号：US20090102009A1

公开(公告)日：2009-04-23

申请号：US12286760

申请日：2008-10-02

申请人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

发明人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L27/115 ,  H01L21/76232 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

摘要翻译： 提供半导体器件和形成半导体器件的方法。 半导体器件包括其边缘是弯曲的有源区域。 半导体器件包括在有源区上的栅极绝缘层，浮栅，栅极层间介质层和控制栅极线。 半导体器件包括在相邻浮动栅极之间具有凹形顶表面的氧化物图案。 控制栅极可以通过氧化物图案与有源区足够间隔开。 该方法可以提供一种半导体器件，其包括再氧化工艺，具有弯曲边缘的有源区和具有弯曲凹形形状的顶表面的氧化物图案。

公开(公告)号：US10811421B2

公开(公告)日：2020-10-20

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/31 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20180026041A1

公开(公告)日：2018-01-25

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/1157 ,  H01L23/31 ,  H01L27/11582

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20160293627A1

公开(公告)日：2016-10-06

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

摘要翻译： 提供半导体存储器件及其制造方法。 该装置可以包括二维布置在基板上并从基板垂直延伸的垂直通道结构。 该装置还可以包括在垂直通道结构上的位线，并且每个位线可以共同连接到沿第一方向布置的垂直通道结构。 该装置还可以包括在与第一方向相交的第二方向上在垂直通道结构之间延伸的公共源极线和与位线设置在相同垂直电平并将公共源极线彼此电连接的源极捆扎线 。

公开(公告)号：US09330966B2

公开(公告)日：2016-05-03

申请号：US13313172

申请日：2011-12-07

申请人： Sun-Young Kim ,  Jun-Eui Song ,  Tae-Wan Lim

发明人： Sun-Young Kim ,  Jun-Eui Song ,  Tae-Wan Lim

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L27/11521 ,  H01L2221/1031

摘要： Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括在第一绝缘图案上形成第二绝缘图案。 第一绝缘图案可以覆盖多个导电结构，并且其中可以包括孔。 第二绝缘图案可以包括与孔连接的沟槽。 所述方法还可以包括在孔和沟槽的侧壁上形成间隔物。 该方法还可以包括在孔和沟槽中形成布线结构。

公开(公告)号：US20110201189A1

公开(公告)日：2011-08-18

申请号：US13094229

申请日：2011-04-26

申请人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

发明人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L21/76232 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

摘要翻译： 提供半导体器件和形成半导体器件的方法。 半导体器件包括其边缘是弯曲的有源区域。 半导体器件包括在有源区上的栅极绝缘层，浮栅，栅极层间介质层和控制栅极线。 半导体器件包括在相邻浮动栅极之间具有凹形顶表面的氧化物图案。 控制栅极可以通过氧化物图案与有源区足够间隔开。 该方法可以提供一种半导体器件，其包括再氧化工艺，具有弯曲边缘的有源区和具有弯曲凹形形状的顶表面的氧化物图案。

公开(公告)号：US07952134B2

公开(公告)日：2011-05-31

申请号：US12286760

申请日：2008-10-02

申请人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

发明人： Ki-Yeol Byun ,  Chan-Kwang Park ,  Jae-Hwan Moon ,  Tae-Wan Lim ,  Seung-Ah Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/76232 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

摘要翻译： 提供半导体器件和形成半导体器件的方法。 半导体器件包括其边缘是弯曲的有源区域。 半导体器件包括在有源区上的栅极绝缘层，浮栅，栅极层间介质层和控制栅极线。 半导体器件包括在相邻浮动栅极之间具有凹形顶表面的氧化物图案。 控制栅极可以通过氧化物图案与有源区足够间隔开。 该方法可以提供一种半导体器件，其包括再氧化工艺，具有弯曲边缘的有源区和具有弯曲凹形形状的顶表面的氧化物图案。