公开(公告)号：US20120278538A1

公开(公告)日：2012-11-01

申请号：US13421618

申请日：2012-03-15

申请人： Takahiro Nango ,  Hiroyuki Moro ,  Motohiro Matsuyama ,  Kiyotaka Iwasaki

发明人： Takahiro Nango ,  Hiroyuki Moro ,  Motohiro Matsuyama ,  Kiyotaka Iwasaki

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals.

摘要翻译： 根据一个实施例，数据存储装置包括存储器模块和控制器。 存储器模块具有多个闪存芯片。 将数据写入或读取具有特定页面大小的每个闪存芯片作为存取单元。 控制器被配置为分别向闪速存储器芯片提供独立于包含数据和地址的公共信号的存储器控​​制信号，以将大于特定数据大小的数据写入存储器模块。 在存储器模块中，相应的闪存芯片响应于存储器控制信号将数据存储在相同的地址处。

公开(公告)号：US20110320868A1

公开(公告)日：2011-12-29

申请号：US13087177

申请日：2011-04-14

申请人： Takami SUGITA ,  Hiroyuki MORO ,  Takahiro NANGO

发明人： Takami SUGITA ,  Hiroyuki MORO ,  Takahiro NANGO

IPC分类号： G06F11/07

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

摘要翻译： 根据一个实施例，数据存储装置包括读取模块，错误检测器和控制器。 读取模块被配置为从闪速存储器中更准确地读取来自闪存中的重写区域和回写区域的数据。 错误检测器被配置为检测数据读取中的错误（如果有的话）。 控制器被配置为保持重写数据，而不纠正错误检测器在闪存的重写区域中检测到的错误。

公开(公告)号：US20080030386A1

公开(公告)日：2008-02-07

申请号：US11830705

申请日：2007-07-30

申请人： Hideyuki Yamakawa ,  Yukiyasu Tatsuzawa ,  Takayuki Mori ,  Takahiro Nango

发明人： Hideyuki Yamakawa ,  Yukiyasu Tatsuzawa ,  Takayuki Mori ,  Takahiro Nango

IPC分类号： H03M1/10

CPC分类号： H03M1/1071

摘要： An integrated circuit includes an AD converter and a self-test circuit configured to test the AD converter. The self-test circuit includes a clock generator which generates a clock for allowing the AD converter to AD-convert an external sine wave signal externally input, a sine wave generator which generates an internal sine wave signal in digital form, a subtractor which determines a differential signal between the AD-converted external sine wave signal and the internal sine wave signal, a PLL device which allows a phase-locked loop receiving the differential signal as an input to control a phase of the internal sine wave signal such that the internal sine wave signal is in phase with the external sine wave signal, and a root mean square calculator which calculates a root mean square of the differential signal to generate a diagnostic signal corresponding to the AD converter.

摘要翻译： 集成电路包括AD转换器和被配置为测试AD转换器的自检电路。 自检电路包括时钟发生器，其产生用于允许AD转换器对外部输入的外部正弦波信号进行AD转换的时钟，产生数字形式的内部正弦波信号的正弦波发生器，确定 AD转换外部正弦波信号和内部正弦波信号之间的差分信号，允许锁相环接收差分信号作为输入的PLL器件，以控制内部正弦波信号的相位，使得内部正弦波 波信号与外部正弦波信号同相，以及均方根计算器，其计算差分信号的均方根以产生对应于AD转换器的诊断信号。

公开(公告)号：US20070025212A1

公开(公告)日：2007-02-01

申请号：US11493514

申请日：2006-07-27

申请人： Yukiyasu Tatsuzawa ,  Takahiro Nango ,  Hideyuki Yamakawa ,  Koichi Otake ,  Toshihiko Kaneshige ,  Hiroaki Morino

发明人： Yukiyasu Tatsuzawa ,  Takahiro Nango ,  Hideyuki Yamakawa ,  Koichi Otake ,  Toshihiko Kaneshige ,  Hiroaki Morino

IPC分类号： G11B15/52

CPC分类号： G11B20/1833 ,  G11B7/0053 ,  G11B20/1217 ,  G11B20/18 ,  G11B2020/122 ,  G11B2020/1287 ,  G11B2220/2537 ,  G11B2220/2579

摘要： According to one embodiment, there is provided an optical disk apparatus including a detecting unit which reads a reflective light from an optical disk and outputs a read signal, a decoder which decodes the read signal from the detecting unit, an extracting unit which extracts from the read signal the first and second specification information of the same content recorded in first and second areas on the optical disk, a processor which compares the first specification information with the second specification information and processes the specification information based on the comparison result, and a controller which controls the detecting unit or the decoder, based on the specification information processed by the processor.

摘要翻译： 根据一个实施例，提供了一种光盘装置，包括：检测单元，其从光盘读取反射光并输出读取信号;解码器，其对来自检测单元的读取信号进行解码;提取单元，其从 读取信号记录在光盘上的第一和第二区域中记录的相同内容的第一和第二规格信息;处理器，其将第一规格信息与第二规格信息进行比较，并根据比较结果处理规格信息;以及控制器 其基于由处理器处理的规格信息来控制检测单元或解码器。

公开(公告)号：US08583968B2

公开(公告)日：2013-11-12

申请号：US13087177

申请日：2011-04-14

申请人： Takami Sugita ,  Hiroyuki Moro ,  Takahiro Nango

发明人： Takami Sugita ,  Hiroyuki Moro ,  Takahiro Nango

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

摘要翻译： 根据一个实施例，数据存储装置包括读取模块，错误检测器和控制器。 读取模块被配置为从闪速存储器中更准确地读取来自闪存中的重写区域和回写区域的数据。 错误检测器被配置为检测数据读取中的错误（如果有的话）。 控制器被配置为保持重写数据，而不纠正错误检测器在闪存的重写区域中检测到的错误。

公开(公告)号：US20110296084A1

公开(公告)日：2011-12-01

申请号：US13077283

申请日：2011-03-31

申请人： Takahiro NANGO

发明人： Takahiro NANGO

IPC分类号： G06F12/02

CPC分类号： G11C16/08 ,  G11C16/26

摘要： According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.

摘要翻译： 根据一个实施例，数据存储装置包括闪速存储器和用于控制闪速存储器的控制器。 闪存被配置为存储以规定大小为单位的数据。 为了写入小于规定尺寸的数据，控制器首先从已经从任何闪速存储器读取的规定尺寸的每个存储数据项中分离属性数据，然后将属性数据存储到属性数据存储器，最后 将保存数据中包含的用户数据传输到保存数据存储器。

公开(公告)号：US20060005110A1

公开(公告)日：2006-01-05

申请号：US11168305

申请日：2005-06-29

申请人： Takahiro Nango ,  Yukiyasu Tatsuzawa

发明人： Takahiro Nango ,  Yukiyasu Tatsuzawa

IPC分类号： H03M13/00

CPC分类号： G11B20/1866 ,  H03M13/151 ,  H03M13/159 ,  H03M13/2909

摘要： A data processing apparatus may include a memory unit which stores information including sync frame data, a preceding calculation system circuit which makes a syndrome calculation from the information including sync frame data, a retry calculation system circuit which makes a syndrome calculation from information stored in the memory unit, a buffer group which stores a calculation result of the preceding calculation system circuit or that of the retry calculation system circuit, and a correction execution process system circuit which executes error correction for the information including sync frame data according to the calculation result stored in the buffer group.

摘要翻译： 数据处理装置可以包括存储单元，其存储包括同步帧数据的信息，从包括同步帧数据的信息进行校正子计算的先前计算系统电路，从存储在所述同步帧数据中的信息进行校正子计算的重试计算系统电路 存储单元，存储前一个计算系统电路的计算结果或重试计算系统电路的计算结果的缓冲器组以及根据存储的计算结果执行包括同步帧数据的信息的纠错执行处理系统电路 在缓冲组中。

公开(公告)号：US08332579B2

公开(公告)日：2012-12-11

申请号：US13077283

申请日：2011-03-31

申请人： Takahiro Nango

发明人： Takahiro Nango

IPC分类号： G06F12/00

CPC分类号： G11C16/08 ,  G11C16/26

摘要： According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.

摘要翻译： 根据一个实施例，数据存储装置包括闪速存储器和用于控制闪速存储器的控制器。 闪存被配置为存储以规定大小为单位的数据。 为了写入小于规定尺寸的数据，控制器首先从已经从任何闪速存储器读取的规定尺寸的每个存储数据项中分离属性数据，然后将属性数据存储到属性数据存储器，最后 将保存数据中包含的用户数据传输到保存数据存储器。

公开(公告)号：US20120102262A1

公开(公告)日：2012-04-26

申请号：US13205193

申请日：2011-08-08

申请人： Takahiro NANGO ,  Hiroyuki MORO ,  Tohru FUKUDA

发明人： Takahiro NANGO ,  Hiroyuki MORO ,  Tohru FUKUDA

IPC分类号： G06F12/00

CPC分类号： G06F13/1642 ,  G06F3/0656 ,  G11B20/18

摘要： According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

摘要翻译： 根据一个实施例，存储器控制装置包括：通道中的队列; 第一控制器 发电机; 和第二控制器。 队列保存数据的写入命令。 第一控制器导致：（i）当接收到读命令时，直到写入命令保持在队列中，通道彼此同步，写入命令的处理准备好执行，基于读取过程 在写命令之前的read命令; 和（ii）当写入命令的处理准备好执行时，基于写入命令的数据段的通道同步和写入处理。 当通道彼此同步时，发生器基于数据段产生纠错码，并且执行基于写入命令的处理。 第二个控制器将错误校正码写入存储介质。

公开(公告)号：US20080117731A1

公开(公告)日：2008-05-22

申请号：US11848113

申请日：2007-08-30

申请人： Hiroyuki Moro ,  Takahiro Nango ,  Koichi Otake

发明人： Hiroyuki Moro ,  Takahiro Nango ,  Koichi Otake

IPC分类号： G11B7/00

CPC分类号： G11B7/0945 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2579

摘要： According to one embodiment, a data recording and reproducing apparatus includes: a reproduced signal output device reading data recorded on an optical recording medium to output a reproduced signal; and a waveform compensation amount data generating device generating waveform compensation amount data of a recording waveform corresponding to recording data which is to be recorded to the optical recording medium. At the time of recording learning, this data recording and reproducing apparatus integrates, for each pattern, waveform error data which are used as a basis of the generation of the waveform compensation amount data by the waveform compensation amount data generating device, and adjusts output of a pattern instruction signal for instructing which of the patterns is an integration target, so as to integrate, for each pattern, the waveform error data in a target test write area corresponding to an integer number of rotations of the optical recording medium.

摘要翻译： 根据一个实施例，数据记录和再现装置包括：再现信号输出装置，读取记录在光学记录介质上的数据，以输出再现信号; 以及波形补偿量数据生成装置，生成与记录在光记录介质上的记录数据对应的记录波形的波形补偿量数据。 在记录学习时，该数据记录和再现装置针对每个模式对由波形补偿量数据生成装置生成波形补偿量数据的基础的波形误差数据进行了积分，并且调整 用于指示哪个模式是集成目标的模式指令信号，以便针对每个模式将与光学记录介质的整数旋转相对应的目标测试写入区域中的波形误差数据进行积分。