公开(公告)号：US08729778B2

公开(公告)日：2014-05-20

申请号：US13475057

申请日：2012-05-18

申请人： Masanaga Nishikawa ,  Takashi Hase ,  Toshio Nishimura

发明人： Masanaga Nishikawa ,  Takashi Hase ,  Toshio Nishimura

IPC分类号： H01L41/08

CPC分类号： H01L41/083 ,  G02B7/06 ,  G02B7/08 ,  H02N2/002 ,  H02N2/025

摘要： An electromechanical transducer that includes an elongating/contracting member and a driving member. The elongating/contracting member elongates and contracts in response to application of a voltage thereto. The elongating/contracting member has a side surface that is parallel to an elongation/contraction direction. The driving member is provided on the side surface of the elongating/contracting member. The driving member is displaced with elongation and contraction of the elongating/contracting member.

摘要翻译： 一种包括伸长/收缩构件和驱动构件的机电换能器。 延伸/收缩构件响应于施加电压而伸长和收缩。 拉伸/收缩构件具有平行于伸长/收缩方向的侧表面。 驱动构件设置在拉伸/收缩构件的侧表面上。 驱动构件随伸长/收缩构件的伸长和收缩而移动。

公开(公告)号：US07968947B2

公开(公告)日：2011-06-28

申请号：US12086435

申请日：2006-12-26

申请人： Takashi Hase

发明人： Takashi Hase

IPC分类号： H01L27/092 ,  H01L21/70

CPC分类号： H01L21/823871 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

摘要： This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b).

摘要翻译： 本发明提供一种能够通过采用具有均匀组成的栅电极来防止功函偏差的半导体器件，并且由于有效的Vth控制而具有优异的工作特性。 半导体器件的特征在于包括PMOS晶体管，NMOS晶体管，包括具有高介电常数的含Hf绝缘膜的栅极绝缘膜，包括硅化物区域（A）和硅化物区域（B）的线电极， 硅化物区域（A）和（B）包括在硅化反应中用作扩散物质的金属M的硅化物（a），另一个硅化物区域包括与栅极绝缘膜接触的硅化物层（C） 包含金属M的硅化物（b）的硅化物层（C），其具有比硅化物（a）更小的金属M的原子组成比，以及可以基本上防止金属M扩散的掺杂​​剂 硅化物（b）。

公开(公告)号：US07883983B2

公开(公告)日：2011-02-08

申请号：US12467519

申请日：2009-05-18

申请人： Takashi Hase

发明人： Takashi Hase

IPC分类号： H01L21/768

CPC分类号： H01L29/7843 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device, includes: forming a gate insulating film on a semiconductor substrate; forming a first metal film on the gate insulating film; forming a second metal film on the first metal film; and patterning a stacked film of the first and second metal films such that the stacked film is left in a gate electrode formation region and a resistive element formation region. The method further includes: removing the second metal film in the resistive element formation region with protecting a contact hole formation region. The method further includes: forming an interlayer insulating film so as to cover the stacked film; and removing the interlayer insulating film formed in the contact hole formation region to form a contact hole leading to the second metal film.

摘要翻译： 一种制造半导体器件的方法，包括：在半导体衬底上形成栅极绝缘膜; 在栅极绝缘膜上形成第一金属膜; 在所述第一金属膜上形成第二金属膜; 以及图案化第一和第二金属膜的堆叠膜，使得堆叠的膜留在栅电极形成区域和电阻元件形成区域中。 该方法还包括：通过保护接触孔形成区域来去除电阻元件形成区域中的第二金属膜。 该方法还包括：形成层间绝缘膜以覆盖层叠膜; 以及去除形成在接触孔形成区域中的层间绝缘膜，以形成通向第二金属膜的接触孔。

公开(公告)号：US07776673B2

公开(公告)日：2010-08-17

申请号：US12048482

申请日：2008-03-14

申请人： Takashi Hase

发明人： Takashi Hase

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, wherein the method facilitates obtaining a full silicide phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

摘要翻译： 根据本发明，提供一种制造包括PMOS晶体管和NMOS晶体管的半导体器件的方法，其中该方法分别有助于获得用于NMOS晶体管和PMOS晶体管的合适组成的完全硅化物相，具有更少的 掩模层和更少数量的制造步骤。

公开(公告)号：US20100193883A1

公开(公告)日：2010-08-05

申请号：US12699076

申请日：2010-02-03

申请人： TAKASHI HASE

发明人： TAKASHI HASE

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28097 ,  H01L21/28123 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided is a semiconductor device of the present invention including, a substrate; a Hf-containing insulating film (HfSiON film) provided over the semiconductor substrate; a NiSi fully-silicided electrode for blocking diffusion of at least Hf which composes the insulating film and a metal element which composes the fully-silicided gate electrode, provided over the HfSiON film; and a barrier film (SiOC film) provided between HfSiON film and the NiSi fully-silicided electrode so as to be brought into contact with the NiSi fully-silicided electrode, wherein the NiSi fully-silicided electrode contains either an N-type or a P-type impurity segregated in a portion thereof brought into contact with the SiOC film, and the SiOC film has a dielectric constant not larger than that of a silicon oxynitride film, and contains (i) silicon (Si), (ii) carbon (C), and (iii) oxygen (O) or nitrogen (N), as major constituents.

摘要翻译： 本发明的半导体器件包括：衬底; 设置在半导体衬底上的含Hf绝缘膜（HfSiON膜）; 用于阻挡构成绝缘膜的至少Hf的扩散的NiSi全硅化物电极和设置在HfSiON膜上的构成全硅化物栅电极的金属元素; 以及设置在HfSiON膜和NiSi全硅化物电极之间以与NiSi全硅化物电极接触的阻挡膜（SiOC膜），其中NiSi全硅化物电极包含N型或P型 与SiOC膜接触的部分分离，SiOC膜的介电常数不大于氮氧化硅膜的介电常数，并且含有（i）硅（Si），（ii）碳（C ）和（iii）氧（O）或氮（N）作为主要成分。

公开(公告)号：US20090221116A1

公开(公告)日：2009-09-03

申请号：US11990464

申请日：2006-08-29

申请人： Takashi Hase

发明人： Takashi Hase

IPC分类号： H01L21/8238 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545

摘要： Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio.

摘要翻译： 元素特性不利地波动，因为当通过烧结金属/多晶硅结构形成全硅化物栅电极时，所得硅化物的组成根据栅极长度的变化而变化。 由于所得硅化物组合物的元素对元素的不均匀性，元素特性也波动。 通过首先形成具有富金属组成的全硅化物，在其上沉积Si层并烧结组合结构，富金属硅化物中的金属扩散到Si层中，使得Si层转化为硅化物。 因此，整个结构转变成具有较小金属组成比的完全硅化物。

公开(公告)号：US07567014B2

公开(公告)日：2009-07-28

申请号：US10559240

申请日：2005-04-20

申请人： Hitoshi Sakaguchi ,  Hiroaki Kaida ,  Takashi Hase

发明人： Hitoshi Sakaguchi ,  Hiroaki Kaida ,  Takashi Hase

IPC分类号： H01L41/047

CPC分类号： H03H9/0207 ,  H03H9/177

摘要： An energy trap piezoelectric resonator makes use of a harmonic wave in a thickness longitudinal vibration mode and can effectively suppress a spurious fundamental wave in a thickness longitudinal vibration mode without significantly suppressing the harmonic wave that is used for the resonator. The energy trap piezoelectric resonator has a first excitation electrode disposed at an upper surface of a piezoelectric substrate polarized in a thickness direction and a second excitation electrode disposed at a lower surface, and a floating electrode disposed at at least one of the upper surface and/or the lower surface of the piezoelectric substrate so as to extend towards and away from the first excitation electrode with respect to a node of an electric potential distribution based on electric charges generated by the fundamental wave that is propagated when an energy trap vibration portion where the excitation electrodes oppose each other is excited.

摘要翻译： 能量阱压电谐振器利用厚度纵向振动模式的谐波，并且可以有效地抑制厚度纵向振动模式中的杂波基波，而不会显着地抑制用于谐振器的谐波。 能量阱压电谐振器具有设置在厚度方向偏振的压电基板的上表面的第一激励电极和设置在下表面的第二激励电极，以及设置在上表面和/ 或者压电基板的下表面相对于基于由基波产生的电荷而相对于电位分布的节点朝向和远离第一激励电极延伸，当基本波产生的电荷是在能量陷阱振动部分 激发电极彼此相对激发。

公开(公告)号：US07446454B2

公开(公告)日：2008-11-04

申请号：US11605412

申请日：2006-11-29

申请人： Hiroaki Kaida ,  Hitoshi Sakaguchi ,  Takashi Hase ,  Jiro Inoue

发明人： Hiroaki Kaida ,  Hitoshi Sakaguchi ,  Takashi Hase ,  Jiro Inoue

IPC分类号： H01L41/08

CPC分类号： H03H9/177 ,  H03H9/02102

摘要： An energy-trapping-type thickness extensional piezoelectric resonator using a thickness extensional vibration mode having first and second resonance electrodes formed on portions of the top surface and the bottom surface of a piezoelectric substrate that is polarized in the thickness direction thereof, respectively, in which a portion where the first and second resonance electrodes oppose each other is formed as an energy-trapping-type vibration section, wherein, in order to suppress frequency changes of the thickness extensional vibration mode due to temperature, which is a main response using resonance characteristics, a suppression response having a frequency-temperature-change tendency for suppressing frequency changes of the main response due to temperature is brought into close proximity with the main response.

摘要翻译： 一种使用厚度延伸振动模式的能量捕获型厚度延伸压电谐振器，其具有分别在其厚度方向上被偏振的压电基板的顶表面和底表面的部分上形成的第一和第二谐振电极，其中， 第一和第二谐振电极彼此相对的部分形成为能量捕获型振动部分，其中为了抑制作为使用谐振特性的主要响应的温度引起的厚度延伸振动模式的频率变化 具有用于抑制由于温度导致的主响应的频率变化的频率 - 温度变化趋势的抑制响应与主要响应紧密相关。

公开(公告)号：US07291530B2

公开(公告)日：2007-11-06

申请号：US11202032

申请日：2005-08-12

申请人： Takashi Nakagawa ,  Takashi Hase

发明人： Takashi Nakagawa ,  Takashi Hase

IPC分类号： H01L21/8234 ,  H01L21/00

CPC分类号： H01L28/55 ,  H01L28/65

摘要： A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.

摘要翻译： 一种具有电容元件的半导体存储器件的制造方法，所述半导体存储器件具有具有由通式ABO 3 3表示的钙钛矿型晶体结构的电介质层，以及下电极和上电极， 介电层; 在该方法中，使用MOCVD方法在下电极导电层上形成初始核，该初始核包含至少一个与电介质层中的金属元素相同的金属元素，在初始核上使用MOCVD 方法，包含与包含在初始核和电介质层中的金属元素相同的至少一种金属元素的缓冲层的含量高于初始核中包含的该金属元素的含量，并且在 缓冲层，使用MOCVD法，电介质层具有钙钛矿型晶体结构。

公开(公告)号：US20070163675A1

公开(公告)日：2007-07-19

申请号：US11593541

申请日：2006-11-07

申请人： Takashi Hase ,  Yukinobu Murakami ,  Hiroyuki Yasunaka ,  Takayoshi Miyazaki ,  Hiroyuki Kato ,  Kyoji Zaitsu

发明人： Takashi Hase ,  Yukinobu Murakami ,  Hiroyuki Yasunaka ,  Takayoshi Miyazaki ,  Hiroyuki Kato ,  Kyoji Zaitsu

IPC分类号： H01L39/24

CPC分类号： H01L39/2409

摘要： A precursor for manufacturing a Nb3Sn superconducting wire by bronze method, in which plural Nb or Nb-based alloy cores are buried in a Cu—Sn-based alloy base material. The Cu—Sn-based alloy base material comprises Ti and/or Zr in addition to Sn, and these components satisfy the equations (1) and (2) below: 0.4≦(X−15.6)/Y≦1.9  (1) and 15.6

摘要翻译： 通过青铜法制造Nb 3 O 3 Sn超导线的前体，其中多个Nb或Nb基合金芯埋在Cu-Sn基合金基材中。 除了Sn之外，Cu-Sn系合金基材还含有Ti和/或Zr，这些成分满足下述式（1）和（2）：＆lt;线内配方说明=“在线式” end =“lead”？> 0.4 <=（X-15.6）/ Y <= 1.9（1）<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line -formulae description =“In-line Formulas”end =“lead”？>和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“ 在线公式“end =”lead“？> 15.6 其中符号X表示内容 的Sn质量％，符号Y表示Ti和Zr的质量％的总含量。