公开(公告)号：US08219882B2

公开(公告)日：2012-07-10

申请号：US12125042

申请日：2008-05-21

申请人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota ,  Yasuhiro Nakamura

发明人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota ,  Yasuhiro Nakamura

IPC分类号： G11C29/00

CPC分类号： G06F11/1068

摘要： A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

摘要翻译： 存储卡包括非易失性存储器，用于控制存储卡的操作的存储器控​​制器。 存储器控制器能够根据预定协议向外部提供接口，并且以规定的时间间隔或在电力供应连接的定时执行存储器信息的错误检测和校正，而不依赖于读出存储器信息 到外部访问请求。 因此，无需主机装置从存储卡的非易失性存储器中读出存储器信息，可以提高非易失性存储器中的数据保持的可靠性。

公开(公告)号：US08134869B2

公开(公告)日：2012-03-13

申请号：US13206574

申请日：2011-08-10

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

公开(公告)号：US20110292727A1

公开(公告)日：2011-12-01

申请号：US13206574

申请日：2011-08-10

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC分类号： G11C16/10

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

公开(公告)号：US08054743B2

公开(公告)日：2011-11-08

申请号：US12189431

申请日：2008-08-11

申请人： Hosei Matsuoka ,  Takayuki Tamura

发明人： Hosei Matsuoka ,  Takayuki Tamura

IPC分类号： G01R31/08 ,  H04W4/00 ,  H04J3/16

CPC分类号： H04W36/28 ,  H04L69/14 ,  H04L69/324 ,  H04W36/36

摘要： An object of the present invention is to make it possible to appropriately maintain PPP-based communications even in an environment in which the terminal moves and the communication environment continually changes. A mobile communication terminal comprises a plurality of wireless accessing devices for establishing PPP-based communication links for respectively different modes of wireless communications with a fixed communication apparatus, which is a communication partner; a PPP device for combining the established communication links; and a valid wireless LAN searching portion for detecting that wireless communication is possible for a wireless LAN adapter. The PPP device executes control so as to establish communication links for the wireless LAN adapter detected as being capable of wireless communication, and for a L2TP virtual device.

摘要翻译： 本发明的目的在于，即使在终端移动的环境和通信环境持续变化的情况下，也可以适当地维护基于PPP的通信。 一种移动通信终端包括：多个无线接入装置，用于分别与作为通信伙伴的固定通信装置的不同模式的无线通信建立基于PPP的通信链路; 用于组合建立的通信链路的PPP设备; 以及用于检测无线LAN适配器的无线通信的有效的无线LAN搜索部分。 PPP设备执行控制，以建立被检测为能够进行无线通信的无线LAN适配器和L2TP虚拟设备的通信链路。

公开(公告)号：US07616485B2

公开(公告)日：2009-11-10

申请号：US11931881

申请日：2007-10-31

申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/349 ,  G11C29/76 ,  G11C29/88

摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

公开(公告)号：US07581058B2

公开(公告)日：2009-08-25

申请号：US11963913

申请日：2007-12-24

申请人： Yoshinori Takase ,  Keiichi Yoshida ,  Takashi Horii ,  Atsushi Nozoe ,  Takayuki Tamura ,  Tomoyuki Fujisawa ,  Ken Matsubara

发明人： Yoshinori Takase ,  Keiichi Yoshida ,  Takashi Horii ,  Atsushi Nozoe ,  Takayuki Tamura ,  Tomoyuki Fujisawa ,  Ken Matsubara

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/7203 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和 所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

公开(公告)号：US20090012318A1

公开(公告)日：2009-01-08

申请号：US11665024

申请日：2005-10-18

申请人： Hideo Suzuki ,  Takayuki Tamura

发明人： Hideo Suzuki ,  Takayuki Tamura

IPC分类号： C07D493/08 ,  C07C67/08 ,  C07D493/04 ,  C07C69/74 ,  C07C61/04 ,  C07C51/083 ,  C07C67/333

CPC分类号： C07C67/11 ,  C07C51/09 ,  C07C51/56 ,  C07C67/08 ,  C07C67/12 ,  C07C67/333 ,  C07C69/74 ,  C07C2601/04 ,  C07D493/04 ,  C07D493/08 ,  C07C61/04

摘要： A process which comprises reacting a 1,2,3,4-cyclobutanetetracarboxylic-1,2:3,4-dianhydride [1] with an alcohol [2] in the presence of an acid catalyst to obtain a compound [3], isomerizing the compound [3] with a base catalyst into a compound [4], reacting the compound [4] with an organic acid to obtain a compound [5], and reacting the compound [5] with a dehydrating agent to obtain a 1,2,3,4-cyclobutanetetracarboxylic-1,3:2,4-dianhydride: wherein R1 and R2 are each independently hydrogen, halogeno, alkyl of 1 to 10 carbon atoms, halogenated alkyl of 1 to 10 carbon atoms, cycloalkyl of 3 to 8 carbon atoms, phenyl, or cyano; and R3 is alkyl of 1 to 10 carbon atoms.

摘要翻译： 一种方法包括在酸催化剂存在下使1,2,3,4-环丁烷四羧酸-1,2：3,4-二酐[1]与醇[2]反应，得到化合物[3]，异构化 化合物[3]与碱催化剂合成化合物[4]，使化合物[4]与有机酸反应，得到化合物[5]，并使化合物[5]与脱水剂反应，得到1， 2,3,4-环丁烷四羧酸-1,3：2,4-二酐：其中R1和R2各自独立地为氢，卤代，1-10个碳原子的烷基，1-10个碳原子的卤代烷基，3〜 8个碳原子，苯基或氰基; 并且R 3是1至10个碳原子的烷基。

公开(公告)号：US20080037322A1

公开(公告)日：2008-02-14

申请号：US11870196

申请日：2007-10-10

申请人： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

发明人： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

公开(公告)号：US07290198B2

公开(公告)日：2007-10-30

申请号：US11504016

申请日：2006-08-15

申请人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

发明人： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC分类号： G11C29/00 ,  G11C16/04 ,  G06F12/00

CPC分类号： G11C29/76 ,  G06F11/1068 ,  G06F13/1673 ,  G11C5/04 ,  G11C29/72 ,  G11C2029/0409

摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

公开(公告)号：US20070035998A1

公开(公告)日：2007-02-15

申请号：US11581690

申请日：2006-10-17

申请人： Takayuki Tamura ,  Yoshinori Takase ,  Shinichi Shuto ,  Yasuhiro Nakamura ,  Chiaki Kumahara

发明人： Takayuki Tamura ,  Yoshinori Takase ,  Shinichi Shuto ,  Yasuhiro Nakamura ,  Chiaki Kumahara

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C2211/5641

摘要： Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of outputting information read from a nonvolatile memory cell as 1-bit information and a second reading operation of outputting the read information as 2-bit information. A controller performs the first reading operation to read first information from the nonvolatile memory and performs the second reading operation to read second information. The reading speed of the first reading operation is faster than that of the second reading operation. In writing to a first area to be read, by using either a voltage in the upper-limit threshold voltage distribution or a voltage in the lower-limit threshold voltage distribution as a threshold voltage, resistance to a retention error of the first information is improved.

摘要翻译： 公开了一种非易失性存储装置，其中安装了非易失性存储器和控制器，并且实现了读/写速度的改进的性能和改进的保持误差的抵抗力。 非易失性存储器可以存储两位以上的信息，并且可以执行将从非易失性存储单元读取的信息作为1位信息输出的第一读取操作和作为2位信息输出读取信息的第二读取操作。 控制器执行第一读取操作以从非易失性存储器读取第一信息，并执行第二读取操作以读取第二信息。 第一读取操作的读取速度比第二读取操作的读取速度更快。 在写入要读取的第一区域中，通过使用上限阈值电压分布中的电压或下限阈值电压分布中的电压作为阈值电压，改善对第一信息的保留误差的抵抗力 。