公开(公告)号：US07158413B2

公开(公告)日：2007-01-02

申请号：US11111870

申请日：2005-04-22

申请人： Nozomi Kasai ,  Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Nozomi Kasai ,  Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

摘要翻译： 半导体存储器件包括存储单元，写位线，读位线，锁存电路，n沟道MOS晶体管和电压设定电路。 存储单元包括具有电荷累积层和控制栅极的第一MOS晶体管。 第一个MOS晶体管共同连接到写入位线和读取位线。 为写位线提供锁存电路，并保存存储单元的写入数据。 在数据锁存操作中，n沟道MOS晶体管将“1”数据传送到锁存电路。 在读取操作中，电压设置电路将与“0”数据相对应的电位提供给写入位线。 在数据锁存操作中，与写入“0”数据的写入位线相对应的写位线对应的锁存电路在读操作中锁存提供给写位线的电位。

公开(公告)号：US07342843B2

公开(公告)日：2008-03-11

申请号：US11110715

申请日：2005-04-21

申请人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C17/18

CPC分类号： G11C29/80 ,  G11C7/18 ,  G11C16/0433 ,  G11C29/789

摘要： A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

摘要翻译： 一种半导体集成电路器件包括半导体存储器电路，其包括其中集成有正常单元的存储单元阵列和其中存储存储半导体存储器电路的操作信息的熔丝单元的熔丝电路。 熔丝单元是具有电荷存储层的单元晶体管和选择单元晶体管的选择晶体管的2晶体管型存储单元。

公开(公告)号：US07280407B2

公开(公告)日：2007-10-09

申请号：US11087576

申请日：2005-03-24

申请人： Akira Umezawa ,  Yoshiharu Hirata ,  Takuya Fujimoto ,  Yoshiaki Hashiba

发明人： Akira Umezawa ,  Yoshiharu Hirata ,  Takuya Fujimoto ,  Yoshiaki Hashiba

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C5/147 ,  G11C5/145 ,  G11C16/12

摘要： A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，字线，第一电荷泵电路和放电电路。 存储单元具有包括浮置栅极和控制栅极的堆叠栅极的第一MOS晶体管。 存储单元阵列包括排列成矩阵的存储单元。 字线通常连接在同一行中的第一MOS晶体管的控制栅极。 第一电荷泵电路被激活，并且在写入操作和擦除操作中产生第一电压。 第一电压供应阱区或字线。 放电电路当第一电荷泵电路被去激活时，将由第一电荷泵电路产生的电荷放电到地或电源电位，同时使电流流到第一电压的输出节点。

公开(公告)号：US20050243628A1

公开(公告)日：2005-11-03

申请号：US11111870

申请日：2005-04-22

申请人： Nozomi Kasai ,  Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Nozomi Kasai ,  Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

摘要翻译： 半导体存储器件包括存储单元，写位线，读位线，锁存电路，n沟道MOS晶体管和电压设定电路。 存储单元包括具有电荷累积层和控制栅极的第一MOS晶体管。 第一个MOS晶体管共同连接到写位线和读位线。 为写位线提供锁存电路，并保存存储单元的写入数据。 在数据锁存操作中，n沟道MOS晶体管将“1”数据传送到锁存电路。 在读取操作中，电压设置电路将与“0”数据相对应的电位提供给写入位线。 在数据锁存操作中，与写入“0”数据的写入位线相对应的写位线对应的锁存电路在读操作中锁存提供给写位线的电位。

公开(公告)号：US20050237842A1

公开(公告)日：2005-10-27

申请号：US11110715

申请日：2005-04-21

申请人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C7/18 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/80 ,  G11C7/18 ,  G11C16/0433 ,  G11C29/789

摘要： A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

摘要翻译： 一种半导体集成电路器件包括半导体存储器电路，其包括其中集成有正常单元的存储单元阵列和其中存储存储半导体存储器电路的操作信息的熔丝单元的熔丝电路。 熔丝单元是具有电荷存储层的单元晶体管和选择单元晶体管的选择晶体管的2晶体管型存储单元。

公开(公告)号：US20050237824A1

公开(公告)日：2005-10-27

申请号：US11087576

申请日：2005-03-24

申请人： Akira Umezawa ,  Yoshiharu Hirata ,  Takuya Fujimoto ,  Yoshiaki Hashiba

发明人： Akira Umezawa ,  Yoshiharu Hirata ,  Takuya Fujimoto ,  Yoshiaki Hashiba

IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/12

CPC分类号： G11C5/147 ,  G11C5/145 ,  G11C16/12

摘要： A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，字线，第一电荷泵电路和放电电路。 存储单元具有包括浮置栅极和控制栅极的堆叠栅极的第一MOS晶体管。 存储单元阵列包括排列成矩阵的存储单元。 字线通常连接在同一行中的第一MOS晶体管的控制栅极。 第一电荷泵电路被激活，并且在写入操作和擦除操作中产生第一电压。 第一电压供应阱区或字线。 放电电路当第一电荷泵电路被去激活时，将由第一电荷泵电路产生的电荷放电到地或电源电位，同时使电流流到第一电压的输出节点。

公开(公告)号：US5675279A

公开(公告)日：1997-10-07

申请号：US667885

申请日：1996-06-20

申请人： Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C11/407 ,  G11C16/06 ,  G11C17/00 ,  H02M3/00 ,  H02M3/07 ,  H03K17/06 ,  H03K3/01 ,  H03K19/094

CPC分类号： H02M3/073 ,  H03K17/063

摘要： A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal. A first clock amplitude control circuit limits the amplitude of the first clock signal to be supplied to the first clock signal supply node to a predetermined level and applies the first amplitude-limited clock signal to the first clock signal supply node. A second clock amplitude control circuit limits the amplitude of the second clock signal to be supplied to the second clock signal supply node to a predetermined level and applies the second amplitude-limited clock signal to the second clock signal supply node.

摘要翻译： 一种升压电路，具有在输入电压节点和升压电压节点之间分级连接的多个建立电路单元。 每个电路单元包括至少两个第一和第二MOS晶体管T1和T2。 第一升压电容器中的每一个连接在第一时钟信号供给节点和第一连接节点之间，多个MOS晶体管中的相应一个奇数MOS晶体管的漏极和栅极通过多个升压器串联连接 电路单元连接在一起。 每个第二升压电容器连接在连接在一起的多个MOS晶体管中的相应一个偶数MOS晶体管的漏极和栅极的第二连接节点和用于向所述第二连接节点提供所述第二连接节点的第二时钟信号供应节点 第二时钟信号的脉冲宽度与第一时钟信号的时间信号不重叠。 第一时钟幅度控制电路将要提供给第一时钟信号提供节点的第一时钟信号的幅度限制到预定电平，并将第一限幅时钟信号施加到第一时钟信号提供节点。 第二时钟幅度控制电路将要提供给第二时钟信号提供节点的第二时钟信号的幅度限制到预定电平，并将第二限幅时钟信号施加到第二时钟信号提供节点。

公开(公告)号：US20090201737A1

公开(公告)日：2009-08-13

申请号：US12368667

申请日：2009-02-10

申请人： Shinji Takeda ,  Yoshiharu Hirata

发明人： Shinji Takeda ,  Yoshiharu Hirata

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second voltages. When writing data to a memory cell, the first voltage is changed to a second value that is lower than a first value. When writing data to a memory cell, the second voltage is changed to a third value that is lower than the second value. The write state machine lowers the second voltage to an intermediate value between the second value and the third value and, while maintaining this intermediate value, lowers the first voltage from the first value to the second value.

摘要翻译： 一种半导体存储器件，包括：写入电路，包括由具有提供有第一电压的正侧电源端子和被提供有第二电压的负侧电源端子的两个反相器构成的锁存电路; 以及控制第一和第二电压的写状态机。 当将数据写入存储单元时，将第一电压改变为低于第一值的第二值。 当将数据写入存储单元时，第二电压被改变为低于第二值的第三值。 写状态机将第二电压降低到第二值和第三值之间的中间值，并且在保持该中间值的同时，将第一电压从第一值降低到第二值。

公开(公告)号：US20070201299A1

公开(公告)日：2007-08-30

申请号：US11733796

申请日：2007-04-11

申请人： Kazushige Kanda ,  Akira Umezawa ,  Kazuhiko Kakizoe ,  Yoshiaki Hashiba ,  Yoshiharu Hirata

发明人： Kazushige Kanda ,  Akira Umezawa ,  Kazuhiko Kakizoe ,  Yoshiaki Hashiba ,  Yoshiharu Hirata

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115

摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m

摘要翻译： 半导体存储器件包括存储单元阵列，字线和行解码器。 存储单元阵列包括排列成矩阵的存储单元。 存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。 字线连接第一MOS晶体管的控制栅极。 行解码器包括第一地址解码电路，第二地址解码电路和传输门。 第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

公开(公告)号：US08331156B2

公开(公告)日：2012-12-11

申请号：US12882232

申请日：2010-09-15

申请人： Takamichi Kasai ,  Yoshiharu Hirata ,  Kazuaki Isobe ,  Akira Umezawa

发明人： Takamichi Kasai ,  Yoshiharu Hirata ,  Kazuaki Isobe ,  Akira Umezawa

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

摘要翻译： 根据一个实施例，非易失性半导体存储装置包括第一导电类型的第一阱区，第一导电类型的第二阱区，第二导电类型的第三阱区，位线和列解码器。 在第一阱区中形成包括多个存储单元的第一单元阵列。 在第二阱区域中形成包括多个存储单元的第二单元阵列。 第三阱区域包括第一和第二阱区域。 位线连接到包括在第一单元阵列中的存储单元和包括在第二单元阵列中的存储单元。 列解码器连接到位线。