利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.01 秒)

    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5424989A

    公开(公告)日：1995-06-13

    申请号：US109488

    申请日：1993-08-20

    申请人： Norio Hagiwara ,  Kazuhisa Sakihama

    发明人： Norio Hagiwara ,  Kazuhisa Sakihama

    IPC分类号： G11C29/00 ,  G11C29/12 ,  G11C29/24 ,  G11C29/42 ,  G11C13/00

    CPC分类号： G11C29/24

    摘要： A semiconductor memory device having information data storing cells and error correction data storing memory cells. When information data is inputted, error correction data related to the information data is formed. In a usual use, the information data and the error correction data are stored in the corresponding memory cells. An external test signal, inputted as the information data, can be stored in the error correction data storing memory cells by a write control signal. In a usual use, the information data stored in the information data storing cells are outputted, as they are or corrected if erroneous. The test signal stored in the error correction data storing memory can be outputted by an output control signal.

    摘要翻译： 具有存储单元的信息数据和存储单元的误差校正数据的半导体存储器件。 当输入信息数据时，形成与信息数据相关的纠错数据。 在通常的使用中，信息数据和纠错数据被存储在相应的存储单元中。 作为信息数据输入的外部测试信号可以通过写控制信号存储在纠错数据存储存储单元中。 在通常的使用中，存储在信息数据存储单元中的信息数据被原样输出或者如果错误地被校正。 可以通过输出控制信号输出存储在纠错数据存储存储器中的测试信号。

    Oscillation circuit
    2.
    发明授权
    Oscillation circuit 失效

    公开(公告)号：US4918408A

    公开(公告)日：1990-04-17

    申请号：US284524

    申请日：1988-12-15

    申请人： Kazuhisa Sakihama ,  Takuya Fujimoto ,  Akihiro Sueda

    发明人： Kazuhisa Sakihama ,  Takuya Fujimoto ,  Akihiro Sueda

    IPC分类号： H03B5/36 ,  H03K3/014 ,  H03K3/03

    CPC分类号： H03K3/014 ,  H03K3/0307

    摘要： An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.

    Method of designing semiconductor chip and program for use in designing semiconductor chip
    3.
    发明申请
    Method of designing semiconductor chip and program for use in designing semiconductor chip 有权

    公开(公告)号：US20060193186A1

    公开(公告)日：2006-08-31

    申请号：US11357641

    申请日：2006-02-16

    申请人： Kazuhisa Sakihama ,  Toru Takahashi

    发明人： Kazuhisa Sakihama ,  Toru Takahashi

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G06F17/5068

    摘要： Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list to be used upon replacing the plurality of types of first standard cells is generated. Automatic placement is performed by using the plurality of types of first standard cells. A certain type of a first standard cell is selected from the plurality of types of first standard cells according to a priority order in the generated list. The selected type of a first standard cell is replaced with a corresponding type of a second standard cell.

    Method of designing semiconductor chip and program for use in designing semiconductor chip
    5.
    发明授权
    Method of designing semiconductor chip and program for use in designing semiconductor chip 有权
    设计半导体芯片的方法和程序用于设计半导体芯片

    公开(公告)号：US07509612B2

    公开(公告)日：2009-03-24

    申请号：US11357641

    申请日：2006-02-16

    申请人： Kazuhisa Sakihama ,  Toru Takahashi

    发明人： Kazuhisa Sakihama ,  Toru Takahashi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list to be used upon replacing the plurality of types of first standard cells is generated. Automatic placement is performed by using the plurality of types of first standard cells. A certain type of a first standard cell is selected from the plurality of types of first standard cells according to a priority order in the generated list. The selected type of a first standard cell is replaced with a corresponding type of a second standard cell.

    摘要翻译： 在设计标准单元型半导体芯片时，准备了与标准单元具有相同功能的多种类型的标准单元和多种类型的成品率改进标准单元，并且具有改变以提高成品率的布局。 生成在更换多种类型的第一标准单元时使用的优​​先顺序列表。 通过使用多种类型的第一标准单元执行自动放置。 根据生成的列表中的优先级顺序，从多种类型的第一标准单元中选择某种类型的第一标准单元。 所选择的第一标准单元的类型被替换为相应类型的第二标准单元。

    ESD protection circuit having a control circuit
    6.
    发明授权
    ESD protection circuit having a control circuit 失效
    ESD保护电路具有控制电路

    公开(公告)号：US06980408B2

    公开(公告)日：2005-12-27

    申请号：US10699827

    申请日：2003-11-04

    申请人： Kazuhisa Sakihama ,  Akira Yamaguchi

    发明人： Kazuhisa Sakihama ,  Akira Yamaguchi

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/10 ,  H02H3/20 ,  H02H3/22 ,  H02H9/00

    CPC分类号： H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An ESD protection circuit comprising a first pad, a second pad, and a clamp circuit. The first pad is used as an external connection terminal to be connected to a semiconductor integrated circuit. The second pad is used as an external connection terminal to be connected to the semiconductor integrated circuit. The clamp circuit is connected between the first pad and the second pad. The ESD protecting circuit further comprises a control circuit. The control circuit controls the clamp circuit, rendering the same conducting or non-conducting.

    摘要翻译： 一种ESD保护电路，包括第一焊盘，第二焊盘和钳位电路。 第一焊盘用作连接到半导体集成电路的外部连接端子。 第二焊盘用作连接到半导体集成电路的外部连接端子。 钳位电路连接在第一焊盘和第二焊盘之间。 ESD保护电路还包括控制电路。 控制电路控制钳位电路，使相同的导通或不导通。