公开(公告)号：US08624264B2

公开(公告)日：2014-01-07

申请号：US13213561

申请日：2011-08-19

Applicant: Tatsuo Shimizu ,  Takashi Shinohe

Inventor： Tatsuo Shimizu ,  Takashi Shinohe

IPC: H01L29/15

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment includes a first electrode and a first silicon carbide (SiC) semiconductor part. The first electrode uses a conductive material and the first silicon carbide (SiC) semiconductor part is connected to the first electrode, in which at least one element of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) is contained in an interface portion with the first electrode in such a way that a surface density thereof peaks, and whose conduction type is a p-type.

Abstract translation: 根据实施例的半导体器件包括第一电极和第一碳化硅（SiC）半导体部件。 第一电极使用导电材料，第一碳化硅（SiC）半导体部分连接到第一电极，其中至少一种元素的镁（Mg），钙（Ca），锶（Sr）和钡（Ba ）包含在与第一电极的界面部分中，使得其表面密度峰值，并且其导电类型是p型。

公开(公告)号：US08476718B2

公开(公告)日：2013-07-02

申请号：US12710851

申请日：2010-02-23

Applicant: Izumi Hirano ,  Yuichiro Mitani ,  Tatsuo Shimizu ,  Yasushi Nakasaki ,  Akiko Masada ,  Shigeto Fukatsu ,  Masahiro Koike

Inventor： Izumi Hirano ,  Yuichiro Mitani ,  Tatsuo Shimizu ,  Yasushi Nakasaki ,  Akiko Masada ,  Shigeto Fukatsu ,  Masahiro Koike

IPC: H01L21/02

CPC classification number: H01L29/7833 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.

Abstract translation: 半导体器件包括：MISFET，包括：半导体层，包括形成在其中的半导体区域; 形成在所述半导体区域上方的栅极绝缘膜，并且包括含有金属和氧的金属氧化物层，所述金属氧化物层中所含的金属为选自Hf和Zr中的至少一种，所述金属氧化物层还包含至少一种元素 选自Ru，Cr，Os，V，Tc和Nb的金属氧化物层，金属氧化物层具有捕获或释放由元素包含形成的电荷的部位，金属氧化物层中的元素的密度在该范围内 1×1015cm-3至2.96×1020cm-3，这些位置被分配成具有比金属氧化物层的中心更靠近半导体区域的峰; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US08330201B2

公开(公告)日：2012-12-11

申请号：US11854090

申请日：2007-09-12

Applicant: Tatsuo Shimizu ,  Koichi Muraoka

Inventor： Tatsuo Shimizu ,  Koichi Muraoka

IPC: H01L29/76

CPC classification number: H01L29/4234 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.

Abstract translation: 提供了一种具有电荷累积层的非易失性半导体存储器，其中使用具有足够高的氮化硅（例如Ti氧化物，Zr氧化物或Hf氧化物）的介电常数的金属氧化物作为 碱性物质和适量的高价物质，其价态增加两个或更多（VI价），以产生能使电子相对于基材进出的陷阱水平。

公开(公告)号：US20120228630A1

公开(公告)日：2012-09-13

申请号：US13213561

申请日：2011-08-19

Applicant: Tatsuo SHIMIZU ,  Takashi Shinohe

Inventor： Tatsuo SHIMIZU ,  Takashi Shinohe

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment includes a first electrode and a first silicon carbide (SiC) semiconductor part. The first electrode uses a conductive material and the first silicon carbide (SiC) semiconductor part is connected to the first electrode, in which at least one element of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) is contained in an interface portion with the first electrode in such a way that a surface density thereof peaks, and whose conduction type is a p-type.

Abstract translation: 根据实施例的半导体器件包括第一电极和第一碳化硅（SiC）半导体部件。 第一电极使用导电材料，第一碳化硅（SiC）半导体部分连接到第一电极，其中至少一种元素的镁（Mg），钙（Ca），锶（Sr）和钡（Ba ）包含在与第一电极的界面部分中，使得其表面密度峰值，并且其导电类型是p型。

公开(公告)号：US08121544B2

公开(公告)日：2012-02-21

申请号：US12427246

申请日：2009-04-21

Applicant: Tatsuo Shimizu ,  Takeyuki Fujii ,  Satoru Ooshima ,  Hidenobu Kakioka ,  Katsunori Ishii

Inventor： Tatsuo Shimizu ,  Takeyuki Fujii ,  Satoru Ooshima ,  Hidenobu Kakioka ,  Katsunori Ishii

IPC: H04B5/00 ,  H01Q13/10

CPC classification number: H01Q13/10 ,  H01Q13/206

Abstract: An antenna apparatus for use in a transmitter or a receiver in a communication system. The antenna apparatus includes: a dielectric substrate having a conductor layer on one of surfaces; and a slot antenna including an antenna electrode formed on the one surface and disposed substantially at the center, a grounded conductive surface surrounding the antenna electrode, and a slot transmission line made by a gap between the antenna electrode and the grounded conductive surface.

Abstract translation: 一种用于通信系统中的发射机或接收机中的天线装置。 所述天线装置包括：电介质基板，在一个表面上具有导体层; 以及缝隙天线，其包括形成在所述一个表面上且基本上位于中心的天线电极，围绕所述天线电极的接地导电表面以及由所述天线电极和所述接地导电表面之间的间隙形成的槽传输线。

公开(公告)号：US20110254062A1

公开(公告)日：2011-10-20

申请号：US13042590

申请日：2011-03-08

Applicant: Tatsuo Shimizu ,  Atsuhiro Kinoshita ,  Hirotaka Nishino

Inventor： Tatsuo Shimizu ,  Atsuhiro Kinoshita ,  Hirotaka Nishino

IPC: H01L29/772 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A field effect transistor which can operate at a low threshold value includes: an n-type semiconductor region; a source region and a drain region separately formed in the n-type semiconductor region; a first insulating film formed in the semiconductor region between the source region and the drain region and containing silicon and oxygen; a second insulating film formed on the first insulating film and containing at least one material selected from Hf, Zr, and Ti and oxygen; and a gate electrode formed on the second insulating film. Ge is doped in an interface region including an interface between the first insulating film and the second insulating film, and an area density of the Ge has a peak on a first insulating film side in the interface region.

Abstract translation: 可以以低阈值工作的场效应晶体管包括：n型半导体区域; 分别形成在所述n型半导体区域中的源极区域和漏极区域; 形成在源极区域和漏极区域之间并且含有硅和氧的半导体区域中的第一绝缘膜; 形成在所述第一绝缘膜上并且包含选自Hf，Zr和Ti中的至少一种材料和氧的第二绝缘膜; 以及形成在所述第二绝缘膜上的栅电极。 Ge掺杂在包括第一绝缘膜和第二绝缘膜之间的界面的界面区域中，Ge的面密度在界面区域的第一绝缘膜侧具有峰值。

公开(公告)号：US07898015B2

公开(公告)日：2011-03-01

申请号：US11689301

申请日：2007-03-21

Applicant: Tatsuo Shimizu ,  Masato Koyama

Inventor： Tatsuo Shimizu ,  Masato Koyama

IPC: H01L29/94

CPC classification number: H01L21/31155 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/28282 ,  H01L28/40 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  Y10T428/12 ,  H01L2924/00

Abstract: An insulating film includes a first metal, oxygen, fluorine and one of a second metal or nitrogen, and satisfies {k×[X]−[F]}/2≦8.4 atomic %, wherein the fluorine amount [F], the one element amount [X], and a valence number difference k between the first and second metals or between oxygen and nitrogen.

Abstract translation: 绝缘膜包括第一金属，氧，氟和第二金属或氮之一，并且满足{k×[X] - [F]} / 2＆nlE; 8.4原子％，其中氟量[F] 元素量[X]和第一和第二金属之间或氧和氮之间的价数差k。

公开(公告)号：US20110035917A1

公开(公告)日：2011-02-17

申请号：US12847388

申请日：2010-07-30

Applicant: Tatsuo Shimizu ,  Takio NAKAMURA ,  Akihiro Goto ,  Yuki Noguchi

Inventor： Tatsuo Shimizu ,  Takio NAKAMURA ,  Akihiro Goto ,  Yuki Noguchi

IPC: B23Q39/02

CPC classification number: B23Q1/5431 ,  B23Q16/102 ,  B23Q39/024 ,  B23Q2039/004 ,  B23Q2220/002 ,  Y10T29/5152 ,  Y10T29/5154 ,  Y10T29/5155 ,  Y10T29/5158 ,  Y10T29/5165 ,  Y10T74/14 ,  Y10T74/1494 ,  Y10T82/2506 ,  Y10T82/2508 ,  Y10T408/37

Abstract: According to the present invention, there is provided an automatic rotating-type turret device for work machinery, in which a lift-type turret is not used. The configuration makes it possible for a clutch device to lock a turret using one drive device (actuator), and generates a wedge effect, thereby obviating the need for a large driving force capable of directly countering a load during cutting operation. The turret can even be locked using air or a small driving force generated by a motor and obviates the need for hydraulics. The automatic rotating-type turret device for work machinery is provided with an axial-direction slide body 7, which is advanced or retracted in the direction of the axis of rotation of the turret 3 by the drive device 5 advancing or retracting the drive body 6 in a direction orthogonal to the direction of rotation axis; and a clutch device 4 that is engaged or disengaged by the axial-direction slide body 7 being advanced or retracted, the turret 3 being of a non-lift-type, and there being provided to the drive body 6 a tapering action part 8 for generating an expanding action caused by the movement of the drive body 6 and pressingly sliding the axial-direction slide body 7 against the turret stage 1.

Abstract translation: 根据本发明，提供了一种用于工作机械的自动旋转式转塔装置，其中不使用升降式转塔。 该构造使得离合器装置可以使用一个驱动装置（致动器）锁定转台，并且产生楔形效应，从而避免需要能够在切割操作期间直接抵抗负载的大的驱动力。 转塔甚至可以使用空气或由电机产生的小驱动力进行锁定，从而避免了液压的需要。 用于作业机械的自动旋转式转塔装置设置有轴向滑动体7，该轴向滑动体7通过驱动装置5沿着转台轴线的旋转方向前进或后退，该驱动装置5使驱动体6前进或缩回 在与旋转轴线方向正交的方向上; 并且通过前进或后退的轴向滑动体7接合或离开的离合器装置4，转塔3是非升降式的，并且在驱动体6上设置有锥形作用部8，该作用部8用于 产生由驱动体6的移动引起的膨胀作用，并将轴向滑动体7按压地滑动到转台1上。

公开(公告)号：US07763934B2

公开(公告)日：2010-07-27

申请号：US12051274

申请日：2008-03-19

Applicant: Tatsuo Shimizu ,  Koichi Muraoka

Inventor： Tatsuo Shimizu ,  Koichi Muraoka

IPC: H01L27/108

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/785

Abstract: A metal oxide having a sufficiently higher dielectric constant than silicon nitride, such as Ti oxide, Zr oxide, or Hf oxide is used as base material, and in order to generate a trap level capable of moving in and out electrons therein, a high-valence substance of valence of 2 or more (that is, valence VI or higher) is added by a proper amount, and to control the trap level, a proper amount of nitrogen (carbon, boron, or low-valence substance) is added, and thus a nonvolatile semiconductor memory having a charge accumulating layer is obtained.

Abstract translation: 作为基材，使用具有比氮化硅足够高的介电常数的金属氧化物，例如Ti氧化物，Zr氧化物或Hf氧化物，为了产生能够进出电子的陷阱电平， 2价以上的化合价物质（即VI价以上）加入适当的量，为了控制捕获量，加入适量的氮（碳，硼或低价物质） 从而获得具有电荷累积层的非易失性半导体存储器。

公开(公告)号：US07750364B2

公开(公告)日：2010-07-06

申请号：US12199148

申请日：2008-08-27

Applicant: Kazushige Yamamoto ,  Tatsuo Shimizu

Inventor： Kazushige Yamamoto ,  Tatsuo Shimizu

IPC: H01L27/15

CPC classification number: H01L33/343

Abstract: A light-emitting device includes an active region, an n-type region, a p-type region, an n-electrode and a p-electrode. The active region is formed from a semiconductor material. The semiconductor material has a tetrahedral structure and includes an impurity. The impurity creates at least two energy levels connected with the allowed transition within a band gap of the semiconductor material. The n-type and p-type regions in contact with the active region are disposed between the n-type and p-type regions. An excitation element is configured to inject an electron from the n-type region and inject a hole from the p-type region so as to generate an electron-hole pair in the active region. The active region has a thickness no less than an atomic distance of the semiconductor and no more than 5 nm.

Abstract translation: 发光器件包括有源区，n型区，p型区，n电极和p电极。 有源区由半导体材料形成。 半导体材料具有四面体结构并且包括杂质。 杂质产生与半导体材料的带隙内允许的过渡相连的至少两个能级。 与有源区接触的n型和p型区设置在n型和p型区之间。 激励元件被配置为从n型区域注入电子并从p型区域注入空穴，以在活性区域中产生电子 - 空穴对。 有源区的厚度不小于半导体的原子距离，不大于5nm。