公开(公告)号：US20080113501A1

公开(公告)日：2008-05-15

申请号：US11971747

申请日：2008-01-09

Applicant: Terrence McDaniel ,  Scott Southwick ,  Fred Fishburn

Inventor： Terrence McDaniel ,  Scott Southwick ,  Fred Fishburn

IPC: H01L21/44

CPC classification number: H01L27/10885 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract translation: 本发明包括形成半导体结构的方法，其中在位线之间形成导电结构以与存储节点接触电连接。 位线可以形成在具有多边形顶部的沟槽内。 本发明还包括含有具有多面顶部的沟槽并且在沟槽内包含位线的半导体结构。

公开(公告)号：US20070164350A1

公开(公告)日：2007-07-19

申请号：US11545163

申请日：2006-10-10

Applicant: Frederick Fishburn ,  Terrence McDaniel ,  Richard Lane

Inventor： Frederick Fishburn ,  Terrence McDaniel ,  Richard Lane

IPC: H01L29/788 ,  H01L29/00

CPC classification number: H01L21/28052 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/1052 ,  H01L27/10873 ,  H01L29/4933 ,  H01L29/66545

Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.

Abstract translation: 用于形成半导体器件的方法在多个晶体管字线和多个导电插塞上提供硅化物层。 在一个实施例中，通过使用单个掩模形成字线，字线上的一个或多个牺牲电介质层，导电插塞和导电增强层。 还描述了可以使用本发明方法的一个实施例形成的过程中半导体器件。

公开(公告)号：US20060228880A1

公开(公告)日：2006-10-12

申请号：US11099972

申请日：2005-04-06

Applicant: Terrence McDaniel ,  Scott Southwick ,  Fred Fishburn

Inventor： Terrence McDaniel ,  Scott Southwick ,  Fred Fishburn

IPC: H01L21/4763

CPC classification number: H01L27/10885 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract translation: 本发明包括形成半导体结构的方法，其中在位线之间形成导电结构以与存储节点接触电连接。 位线可以形成在具有多边形顶部的沟槽内。 本发明还包括含有具有多面顶部的沟槽并且在沟槽内包含位线的半导体结构。

公开(公告)号：US20060046398A1

公开(公告)日：2006-03-02

申请号：US10932327

申请日：2004-09-01

Applicant: Terrence McDaniel ,  Sandra Tagg ,  Fred Fishburn

Inventor： Terrence McDaniel ,  Sandra Tagg ,  Fred Fishburn

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/8238

CPC classification number: H01L23/48 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

公开(公告)号：US06258709B1

公开(公告)日：2001-07-10

申请号：US09589903

申请日：2000-06-07

Applicant: Terrence McDaniel

Inventor： Terrence McDaniel

IPC: H01L214763

CPC classification number: H01L21/76885 ,  H01L21/32136 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for the formation of electrical interconnect lines by a selective metal etch to form electrical interconnections between different layers in a semiconductor device is provided. The process eliminates the need to form vias between conductive layers in the structure by etching through an oxide layer. The resulting structure provides superior electrical contacts between electrically conductive features on different layers of a semiconductor device. Additionally, the process produces self-aligned vias, thereby eliminating misalignment problems and the need to pattern surrounds onto the M1 layer in a semiconductor stack or any other lower level metal.

Abstract translation: 提供了通过选择性金属蚀刻形成电互连线以在半导体器件中的不同层之间形成电互连的工艺。 该方法消除了通过蚀刻通过氧化物层在结构中的导电层之间形成通孔的需要。 所得结构在半导体器件的不同层上的导电特征之间提供优异的电接触。 此外，该工艺产生自对准的通孔，从而消除了未对准的问题，并且需要在半导体堆叠或任何其它较低级别的金属中的M1层上图案化。

公开(公告)号：US07902057B2

公开(公告)日：2011-03-08

申请号：US11831296

申请日：2007-07-31

Applicant: Terrence McDaniel

Inventor： Terrence McDaniel

IPC: H01L21/3205

CPC classification number: H01L29/66795 ,  H01L29/7854

Abstract: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: 披露了Fin-FET器件及其制造方法。 Fin-FET器件包括可以用于在源极区域和漏极区域之间提供沟槽区域的双鳍片。 在一些实施例中，可以通过在衬底的突出区域中的相对侧上形成具有翅片结构的沟槽来形成双翅片。 双翅片可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US07445996B2

公开(公告)日：2008-11-04

申请号：US11074563

申请日：2005-03-08

Applicant: Terrence McDaniel

Inventor： Terrence McDaniel

IPC: H01L21/336

CPC classification number: H01L21/76855 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76877 ,  H01L27/10888 ,  H01L27/10894

Abstract: A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.

Abstract translation: 公开了一种用于在半导体器件（例如DRAM存储器件）的存储单元阵列和外围逻辑电路区域中形成低电阻触点的工艺和装置。 在掩埋位线连接工艺流程中，本发明利用钛的化学气相沉积在外围逻辑电路区域和物理气相沉积的接触结构中形成硅化钛，以提供与聚对苯二甲酸丁酯接触的金属模（金属）钛层 插入半导体器件的存储单元阵列区域，例如根据本发明的DRAM存储器件。 以这种方式，本发明避免了由于存在硅化钛的现象导致的存储单元阵列的多晶硅栓堵塞的潜在缺点，这可能导致器件漏极电流的显着降低，并且在极端情况下导致电不连续性。

公开(公告)号：US20070040224A1

公开(公告)日：2007-02-22

申请号：US11208972

申请日：2005-08-22

Applicant: James Green ,  Terrence McDaniel

Inventor： James Green ,  Terrence McDaniel

IPC: H01L29/94

CPC classification number: H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10808 ,  H01L27/10885

Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Abstract translation: 在制造半导体器件期间使用的方法包括形成掩埋的数字线和触点。 在形成期间，掩埋位线层可以用作掩模以蚀刻电介质层中的一个或多个开口。 然后在电介质层的一个或多个开口中形成导电层，然后将其平坦化以形成一个或多个单独的接触插塞。 接下来，蚀刻掩埋位线层以使埋入的位线层凹陷，并且形成电容器板以接触接触插塞。

公开(公告)号：US08026542B2

公开(公告)日：2011-09-27

申请号：US11512004

申请日：2006-08-29

Applicant: Terrence McDaniel ,  Sandra Tagg ,  Fred Fishburn

Inventor： Terrence McDaniel ,  Sandra Tagg ,  Fred Fishburn

IPC: H01L27/108

CPC classification number: H01L23/48 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract translation: 提供了用于形成存储器件和集成电路的方法，例如由这些方法产生的DRAM电路，结构和器件，以及结合该器件的系统。

公开(公告)号：US20110101429A1

公开(公告)日：2011-05-05

申请号：US12987746

申请日：2011-01-10

Applicant: Terrence McDaniel

Inventor： Terrence McDaniel

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/7854

Abstract: Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-PET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: 披露了Fin-FET器件及其制造方法。 Fin-FET器件包括可以用于在源极区域和漏极区域之间提供沟槽区域的双鳍片。 在一些实施例中，可以通过在衬底的突出区域中的相对侧上形成具有翅片结构的沟槽来形成双翅片。 双翅片可用于形成单栅极，双栅极或三栅极鳍式PET器件。 还公开了包括这种鳍式FET器件的电子系统。