公开(公告)号：US08890580B2

公开(公告)日：2014-11-18

申请号：US13878351

申请日：2011-10-03

Applicant: Jared Zerbe ,  Teva Stone ,  Jihong Ren

Inventor： Jared Zerbe ,  Teva Stone ,  Jihong Ren

IPC: H03B1/00 ,  H03K3/00 ,  H03L7/00 ,  H03K5/1252

CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

公开(公告)号：US20060214742A1

公开(公告)日：2006-09-28

申请号：US11440824

申请日：2006-05-25

Applicant: William Dally ,  Ramin Farjad-Rad ,  John Poulton ,  Thomas Greer ,  Hiok-Tiaq Ng ,  Teva Stone

Inventor： William Dally ,  Ramin Farjad-Rad ,  John Poulton ,  Thomas Greer ,  Hiok-Tiaq Ng ,  Teva Stone

IPC: H03B5/08

CPC classification number: H03L7/0805 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/083 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

公开(公告)号：US20060082399A1

公开(公告)日：2006-04-20

申请号：US11217109

申请日：2005-08-30

Applicant: William Dally ,  Ramin Farjad-Rad ,  Teva Stone ,  Xiaoying Yu ,  John Poulton

Inventor： William Dally ,  Ramin Farjad-Rad ,  Teva Stone ,  Xiaoying Yu ,  John Poulton

IPC: H03B19/00

CPC classification number: H03D13/008 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/0895 ,  H03L7/18 ,  H03L7/191

Abstract: A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.

Abstract translation: 定时信号的相位比较由接收定时信号和窗口信号的组合电路进行，窗口信号识别要比较的定时信号的边缘。 比较可能导致电荷泵浦输出，其可被反馈以控制其中一个定时信号的相位。 相位比较器和电荷泵电路可以包括在乘法器电路中，其中输入信号的相位与乘法信号的边沿的相位直接比较。

公开(公告)号：US20050231291A1

公开(公告)日：2005-10-20

申请号：US11057078

申请日：2005-02-11

Applicant: William Dally ,  Ramin Farjad-Rad ,  John Poulton ,  Thomas Greer ,  Hiok-Tiaq Ng ,  Teva Stone

Inventor： William Dally ,  Ramin Farjad-Rad ,  John Poulton ,  Thomas Greer ,  Hiok-Tiaq Ng ,  Teva Stone

IPC: H03K3/03 ,  H03K3/354 ,  H03L7/00 ,  H03L7/081 ,  H03L7/083 ,  H03L7/091 ,  H03L7/099 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

CPC classification number: H03L7/0805 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/083 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.