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公开(公告)号：US08649475B2
公开(公告)日：2014-02-11
申请号：US13491479
申请日：2012-06-07
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2227 , H03L7/06 , H04L7/0008 , H04L7/046 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
摘要翻译： 为使用固定时钟速率接口的部分速率传输模式提供了系统和方法。 在部分速率模式下，每个数据位连续传输两次或更多次。 接收机使用不进行相位调整的全局时钟来检测复制的传入位。 结果，当系统锁定到从发射机接收的数据的相位时，接收机系统可以以部分数据速率接收数据。
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公开(公告)号：US20060214742A1
公开(公告)日：2006-09-28
申请号：US11440824
申请日：2006-05-25
申请人： William Dally , Ramin Farjad-Rad , John Poulton , Thomas Greer , Hiok-Tiaq Ng , Teva Stone
发明人： William Dally , Ramin Farjad-Rad , John Poulton , Thomas Greer , Hiok-Tiaq Ng , Teva Stone
IPC分类号： H03B5/08
CPC分类号： H03L7/0805 , H03K3/0315 , H03K3/0322 , H03K3/354 , H03L7/07 , H03L7/0812 , H03L7/083 , H03L7/091 , H03L7/0995 , H03L7/0998 , H03L7/20 , H03L7/23 , H03L7/24
摘要： An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.
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公开(公告)号：US20100220828A1
公开(公告)日：2010-09-02
申请号：US12525044
申请日：2008-02-11
申请人： Andrew M. Fuller , John Poulton
发明人： Andrew M. Fuller , John Poulton
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译： 描述电路的实施例。 该电路包括包括第一采样器（312-1）和第二“采样器（312-2）”的接收器电路。 接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。 接收器电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。 该偏移校准电路可以在靠近信号交叉点（410-2）的定时区域中确定给定采样器的当前偏移电压（412），其中时钟数据恢复电路基于当前采样时间抖动 当前偏移电压。 此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。
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公开(公告)号：US20080094109A1
公开(公告)日：2008-04-24
申请号：US11963747
申请日：2007-12-21
申请人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
发明人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
IPC分类号： H03K17/00
CPC分类号： G06F1/06 , G06F1/04 , H03L7/0812 , H03L7/0995 , H03L7/0998
摘要： A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.
摘要翻译： 一种具有第一时钟发生电路，分频器电路和多个多路复用器的宽范围多相时钟发生器。 第一时钟产生电路产生多个第一时钟信号，每个第一时钟信号具有第一频率和多个不同相位角中的相应一个。 分频器电路从第一时钟发生电路接收多个第一时钟信号，并产生多个第二时钟信号，每个具有第二频率和多个不同相位角中的相应一个。 多路复用器各自具有耦合以接收第一时钟信号中的相应一个的第一输入和耦合以接收具有与第一时钟信号之一基本相同的相位角的第二时钟信号中的相应一个的第二输入。
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公开(公告)号：US20050258883A1
公开(公告)日：2005-11-24
申请号：US11001865
申请日：2004-12-01
申请人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
发明人： Ramin Farjad-rad , John Poulton , John Eble , Thomas Greer , Robert Palmer
CPC分类号： G06F1/06 , G06F1/04 , H03L7/0812 , H03L7/0995 , H03L7/0998
摘要： A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.
摘要翻译： 一种具有第一时钟发生电路，分频器电路和多个多路复用器的宽范围多相时钟发生器。 第一时钟产生电路产生多个第一时钟信号，每个第一时钟信号具有第一频率和多个不同相位角中的相应一个。 分频器电路从第一时钟发生电路接收多个第一时钟信号，并产生多个第二时钟信号，每个具有第二频率和多个不同相位角中的相应一个。 多路复用器各自具有耦合以接收第一时钟信号中的相应一个的第一输入和耦合以接收具有与第一时钟信号之一基本相同的相位角的第二时钟信号中的相应一个的第二输入。
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公开(公告)号：US08208593B2
公开(公告)日：2012-06-26
申请号：US12247871
申请日：2008-10-08
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2227 , H03L7/06 , H04L7/0008 , H04L7/046 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
摘要翻译： 为使用固定时钟速率接口的部分速率传输模式提供了系统和方法。 在部分速率模式下，每个数据位连续传输两次或更多次。 接收机使用不进行相位调整的全局时钟来检测复制的传入位。 结果，当系统锁定到从发射机接收的数据的相位时，接收机系统可以以部分数据速率接收数据。
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公开(公告)号：US20090129505A1
公开(公告)日：2009-05-21
申请号：US12247871
申请日：2008-10-08
IPC分类号： H04L27/00
CPC分类号： H04L7/0337 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2227 , H03L7/06 , H04L7/0008 , H04L7/046 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
摘要翻译： 为使用固定时钟速率接口的部分速率传输模式提供了系统和方法。 在部分速率模式下，每个数据位连续传输两次或更多次。 接收机使用不进行相位调整的全局时钟来检测复制的传入位。 结果，当系统锁定到从发射机接收的数据的相位时，接收机系统可以以部分数据速率接收数据。
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公开(公告)号：US20060165185A1
公开(公告)日：2006-07-27
申请号：US11040845
申请日：2005-01-21
申请人： William Dally , John Poulton
发明人： William Dally , John Poulton
IPC分类号： H04B3/00
CPC分类号： H04L25/4904
摘要： A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.
摘要翻译： 数据通信系统包括第一和第二集成电路之间的传输线。 第一集成电路上的编码器对输入数据流进行编码以产生码字序列，其中该序列中的码字是表示输入数据流中的数据的一组码字的成员，并且该组的成员基本上是直流平衡的， 如曼彻斯特编码符号集。 第二集成电路上的积分电路通过将特定符号单元内的正极性的第一间隔积分并且在特定符号单元内积分具有负极性的第二间隔来积分代码字，以产生表示代码字的输出。 感测电路产生输出数据流。
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公开(公告)号：US08199866B2
公开(公告)日：2012-06-12
申请号：US12525044
申请日：2008-02-11
申请人： Andrew M. Fuller , John Poulton
发明人： Andrew M. Fuller , John Poulton
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译： 描述电路的实施例。 该电路包括包括第一采样器（312-1）和第二“采样器（312-2）”的接收器电路。 接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。 接收器电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。 该偏移校准电路可以在靠近信号交叉点（410-2）的定时区域中确定给定采样器的当前偏移电压（412），其中时钟数据恢复电路基于当前采样时间抖动 当前偏移电压。 此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。
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公开(公告)号：US20060236147A1
公开(公告)日：2006-10-19
申请号：US11107121
申请日：2005-04-15
申请人： Scott Best , Stephen Tell , John Poulton
发明人： Scott Best , Stephen Tell , John Poulton
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F2213/0038
摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
摘要翻译： 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。
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