公开(公告)号：US4608669A

公开(公告)日：1986-08-26

申请号：US611817

申请日：1984-05-18

申请人： Walter S. Klara ,  Theodore W. Kwap ,  Victor Marcello ,  Robert A. Rasmussen

发明人： Walter S. Klara ,  Theodore W. Kwap ,  Victor Marcello ,  Robert A. Rasmussen

IPC分类号： G11C29/00 ,  G01R31/26 ,  G01R31/28 ,  G11C7/00 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C29/50 ,  G11C29/56 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10

CPC分类号： G11C29/50012 ,  G11C29/14 ,  G11C29/50 ,  G11C7/22

摘要： An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.

摘要翻译： 公开了一种用于产生用于大规模集成（LSI）芯片或半导体存储器阵列的定时信号的片上装置。 该设备可以在存储器的生产测试期间和在正常功能操作期间使用。 在测试环境中，它允许使用便宜得多的外围测试设备，同时在确定存储器阵列是否满足其定时规范方面提供了更高的精度。 在正常功能操作期间（在测试环境中使用后）使用可提供无缺陷操作的保证。

公开(公告)号：US4529894A

公开(公告)日：1985-07-16

申请号：US273706

申请日：1981-06-15

申请人： Yuen H. Chan ,  James E. Dickerson ,  Walter S. Klara ,  Theodore W. Kwap ,  Joseph M. Mosley

发明人： Yuen H. Chan ,  James E. Dickerson ,  Walter S. Klara ,  Theodore W. Kwap ,  Joseph M. Mosley

IPC分类号： H03K5/12 ,  H03K17/04 ,  H03K19/013 ,  H03K19/086 ,  H03K19/01 ,  H03K19/082

CPC分类号： H03K19/0136

摘要： Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.

摘要翻译： 公开了用于增强逻辑电路性能的手段，更具体地说，用于增强各种逻辑电路的切换速度。 所涉及的是将所谓的“卡扣”或增强型晶体管插入连接到限定基本逻辑电路的输出的公共节点。 在一个示例中，该“捕捉”晶体管的发射极连接到电路中的输出节点，其在常规实践中将在上行转换期间被固定的RC时间常数充电。 然而，根据本发明的改进，由于存储在其中的电荷，“卡扣”晶体管保持导通，尽管关联的逻辑器件被关断。 该电流作为反向基极电流放电，并且输出提供看起来是感应电压尖峰。 效果是临时的电流源可用于对公共节点充电。 结果，显着减少了在输出节点从一个电压电平转到另一个电压电平的过渡时间。