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公开(公告)号：US4529894A
公开(公告)日：1985-07-16
申请号：US273706
申请日：1981-06-15
IPC分类号： H03K5/12 , H03K17/04 , H03K19/013 , H03K19/086 , H03K19/01 , H03K19/082
CPC分类号： H03K19/0136
摘要： Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.
摘要翻译： 公开了用于增强逻辑电路性能的手段，更具体地说，用于增强各种逻辑电路的切换速度。 所涉及的是将所谓的“卡扣”或增强型晶体管插入连接到限定基本逻辑电路的输出的公共节点。 在一个示例中，该“捕捉”晶体管的发射极连接到电路中的输出节点，其在常规实践中将在上行转换期间被固定的RC时间常数充电。 然而，根据本发明的改进，由于存储在其中的电荷，“卡扣”晶体管保持导通，尽管关联的逻辑器件被关断。 该电流作为反向基极电流放电，并且输出提供看起来是感应电压尖峰。 效果是临时的电流源可用于对公共节点充电。 结果，显着减少了在输出节点从一个电压电平转到另一个电压电平的过渡时间。
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2.发明授权Low power programmable clock delay generator with integrated decode function 失效具有集成解码功能的低功耗可编程时钟延迟发生器公开(公告)号：US08237481B2
公开(公告)日：2012-08-07
申请号：US12109728
申请日：2008-04-25
申请人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
发明人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
IPC分类号： H03H11/26 , G06F1/04 , H03K17/284
CPC分类号： H03K5/04 , G06F1/10 , H03K5/133 , H03K2005/00058
摘要： A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.
摘要翻译： 可编程本地时钟缓冲器在时钟输入和延迟时钟输出之间具有单个反相器。 晶体管开关在时钟信号发送状态和非发送状态之间调制单个逆变器级。 延迟选择位的组合控制逆变器相对于经由晶体管开关的时钟输入的发送状态的开始和结束的定时。
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公开(公告)号：US07996620B2
公开(公告)日：2011-08-09
申请号：US11850050
申请日：2007-09-05
申请人： Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
发明人： Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
CPC分类号： G06F12/0895 , G06F12/1045
摘要： A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.
摘要翻译： 高速缓存高性能伪动态地址比较路径将地址分为两个或更多个地址段。 在由静态逻辑元件组成的比较器中，每个段被单独比较。 然后将这些静态比较器中的每一个的输出组合在动态逻辑电路中以产生动态后期选择输出。
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4.发明授权公开(公告)号：US07463537B2
公开(公告)日：2008-12-09
申请号：US11933625
申请日：2007-11-01
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
摘要翻译： 多米诺SRAM全局位选择电路提供了双局域读和写位线对之间的接口到“本地位选择”电路。
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公开(公告)号：US07447964B2
公开(公告)日：2008-11-04
申请号：US11028174
申请日：2005-01-03
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译： 可以在测试电路中使用的测试电路和可编程分压器。 可编程分压器产生可以数字选择的电压差信号。 测试电路可用于测试和表征读出放大器。 可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。 读出放大器设置并输出锁存。 根据预期值检查锁存内容。 可以改变差值电压，重新测试路径以找到通过点和故障点。
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公开(公告)号：US07173875B2
公开(公告)日：2007-02-06
申请号：US10950928
申请日：2004-09-27
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
CPC分类号： G11C11/413 , G11C8/08
摘要： A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability.
摘要翻译： CMOS静态随机存取存储器（SRAM）单元阵列，包括该阵列的集成芯片以及一种以更好的单元稳定性访问阵列中的单元的方法。 连接到阵列中的一半选定单元的位线在单元访问期间浮动以改善单元稳定性。
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公开(公告)号：US07113433B2
公开(公告)日：2006-09-26
申请号：US11054402
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.
摘要翻译： 多米诺SRAM提供有有源上拉PFET器件，它们淹没“读写速度慢但读取速度非常快”，并允许单元从定时不匹配情况中恢复。 这种方法允许传统的“位选择”钳位通过“有线或”PFET上拉晶体管主动地控制“局部选择”。 单独的读写全局“位线”对可以独立优化读写性能。
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公开(公告)号：US4578779A
公开(公告)日：1986-03-25
申请号：US624486
申请日：1984-06-25
申请人： Yuen H. Chan , James R. Struk
发明人： Yuen H. Chan , James R. Struk
IPC分类号： G11C11/414 , G11C11/34 , G11C11/415 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416 , G11C11/415
摘要： The disclosure is directed to an improved random access memory (RAM). More particularly, to improved word line selection circuitry for use in an array employing CTS (Complementary Transistor Switch) type memory cells.
摘要翻译： 本公开针对改进的随机存取存储器（RAM）。 更具体地，涉及用于采用CTS（互补晶体管开关）型存储单元的阵列中的改进字线选择电路。
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9.发明申请Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability 审中-公开用于执行写入操作的方法和电路布置，以及具有写入能力的SRAM阵列公开(公告)号：US20110317478A1
公开(公告)日：2011-12-29
申请号：US13150458
申请日：2011-06-01
申请人： Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
发明人： Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
CPC分类号： G11C11/419 , G11C11/41 , G11C29/1201 , G11C29/48
摘要： An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).
摘要翻译： 公开了一种用于在SRAM阵列（1）的SRAM单元（10）的写入操作期间执行写入操作的改进方法。 该方法包括在SRAM的第一节点（t）或第二节点（c）处的故障导致故障的情况下，通过SRAM阵列（1）的输出节点（C，F）处的数据传播来抑制错误写入 通过使用关于要写入SRAM单元（10）的输入数据（数据，data_b）的信息，读取数据传播路径以在全局位线（gb_t，gb_c）之后保持输出节点（C，F）的单元（10） ），如果SRAM单元（10）的对应节点（c，t）正在执行基于输入数据的失败导致转换（数据， data_b）写入SRAM单元（10）。
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公开(公告)号：US07873891B2
公开(公告)日：2011-01-18
申请号：US12114853
申请日：2008-05-05
申请人： Yuen H. Chan , Rajiv V. Joshi
发明人： Yuen H. Chan , Rajiv V. Joshi
CPC分类号： G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
摘要翻译： 可以在测试电路中使用的测试电路和可编程分压器。 可编程分压器产生可以数字选择的电压差信号。 测试电路可用于测试和表征读出放大器。 可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。 读出放大器设置并输出锁存。 根据预期值检查锁存内容。 可以改变差值电压，重新测试路径以找到通过点和故障点。
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