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1.发明授权Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks 有权用于具有交替相移掩模的减少掩模偏置的分割虚拟填充形状的结构公开(公告)号：US07861208B2
公开(公告)日：2010-12-28
申请号：US11872924
申请日：2007-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density.
摘要翻译： 用于分割的虚拟填充形状的设计结构，方法和系统，用于减少具有交替相移掩模的掩模偏置，或者使用采用修剪掩模的其它双掩模光刻工艺。 设计结构体现在在设计过程中使用的机器可读介质中，该设计结构包括成品半导体设计中不包含设计形状的区域。 该设计结构还包括在预定最终密度的区域中的虚拟填充形状，其中所生成的虚拟形状的尺寸使得它们的局部密度增加到预定值。 此外，相应的修整形状用于暴露虚拟形状的超大部分，有效地将每个虚拟形状修剪回到预定的最终密度。
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公开(公告)号：US07754394B2
公开(公告)日：2010-07-13
申请号：US11559417
申请日：2006-11-14
申请人： Shaun B Crawford , Thomas B Faure , Cuc K Huynh , James P Levin
发明人： Shaun B Crawford , Thomas B Faure , Cuc K Huynh , James P Levin
摘要： Methods for manufacturing a photomask, such as a chrome on glass photomask and a phase shift photomask are provided. A selective main chrome etch and a selective chrome overetch in the fabrication process provides a photomask having improved image quality and provides nominal image size control and image size uniformity across the photomask within current process flows and manufacturing steps. The selective etch process utilizes a main etch where the resist etch selectivity (amount of chrome removed to resist removed) is higher than in the overetch step in which the etch is more selective to removal of the resist layer relative to the chrome layer. To control the etch selectivities the composition of the etchant chemistry and/or the etchant reactor hardware settings (power, voltage, etc.) can be adjusted.
摘要翻译： 提供了制造光掩模的方法，例如玻璃光掩模上的铬和相移光掩模。 选择性主铬蚀刻和制造工艺中的选择性铬过蚀刻提供了具有改进的图像质量的光掩模，并且在当前工艺流程和制造步骤中提供标称图像尺寸控制和光掩模上的图像尺寸均匀性。 选择性蚀刻工艺利用主蚀刻，其中抗蚀剂蚀刻选择性（去除的抗蚀剂去除量）比在蚀刻对于相对于铬层去除抗蚀剂层更有选择性的过蚀刻步骤中更高。 为了控制蚀刻选择性，可以调整蚀刻剂化学成分和/或蚀刻剂反应器硬件设置（功率，电压等）。
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公开(公告)号：US06494966B2
公开(公告)日：2002-12-17
申请号：US09731494
申请日：2000-12-07
IPC分类号： B08B308
摘要： A method for removing contaminants from a substrate surface having a pattern formed on the surface. The method involves rinsing the substrate and pattern with water to remove acid reactive material. The substrate and pattern are then washed with an acid whose concentration is too low to attack the material that forms the pattern. Then the substrate is washed with water to remove the acid.
摘要翻译： 一种用于从表面上形成图案的基板表面去除污染物的方法。 该方法包括用水冲洗底物和图案以除去酸反应性材料。 然后用浓度太低的酸洗涤底物和图案，不会侵蚀形成图案的材料。 然后用水洗涤底物以除去酸。
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公开(公告)号：US06270949B1
公开(公告)日：2001-08-07
申请号：US09529316
申请日：2000-04-11
IPC分类号： G03F730
CPC分类号： G03F7/3021 , G03F7/325
摘要： A method for developing copolymer photosensitive resists wherein a single solvent is used in conjunction with a puddle develop tool. The copolymer resist is ZEP 7000 and the developer is ethyl 3-ethoxy propionate (EEP).
摘要翻译： 用于开发共聚物光敏抗蚀剂的方法，其中单一溶剂与水坑显影工具结合使用。 共聚物抗蚀剂为ZEP 7000，显色剂为3-乙氧基丙酸乙酯（EEP）。
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公开(公告)号：US5318687A
公开(公告)日：1994-06-07
申请号：US927700
申请日：1992-08-07
申请人： Scott A. Estes , Thomas B. Faure , Steven C. Nash
发明人： Scott A. Estes , Thomas B. Faure , Steven C. Nash
IPC分类号： C25D3/48 , G03F1/22 , H01L21/027 , H01L21/30 , C25D13/00
摘要： An electrodeposition process for producing gold masks for X-ray lithography of integrated circuits is disclosed. The process produces a gold layer of tightly controlled grain size and arsenic content which results in minimum stress in the gold film and therefore minimum distortion in the features produced from the mask. The process comprises (a) immersing a substrate in a solution containing from 6 to 9 grams of gold per liter and from 8 to 30 mg of arsenite per liter, and (b) passing an electric current having a current density of 1 to 5 mA per cm.sup.2 through the solution to cause electrodeposition of gold.
摘要翻译： 公开了一种用于制造用于集成电路的X射线光刻的金掩模的电沉积工艺。 该过程产生严格控制的晶粒尺寸和砷含量的金层，其导致金膜中的最小应力，并因此导致由掩模产生的特征的最小变形。 该方法包括（a）将基底浸入含有6-9克金每升和8-30毫克亚砷酸盐/升的溶液中，和（b）使电流密度为1至5mA的电流 每cm 2通过溶液引起电沉积金。
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公开(公告)号：US5160987A
公开(公告)日：1992-11-03
申请号：US656902
申请日：1991-02-15
申请人： Wilber D. Pricer , Thomas B. Faure , Bernard S. Meyerson , William J. Nestork , John R. Turnbull, Jr.
发明人： Wilber D. Pricer , Thomas B. Faure , Bernard S. Meyerson , William J. Nestork , John R. Turnbull, Jr.
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3213 , H01L21/334 , H01L21/8242 , H01L25/065 , H01L27/06 , H01L27/108
CPC分类号： H01L27/108 , H01L21/30608 , H01L21/32137 , H01L25/0657 , H01L27/0688 , H01L27/10844 , H01L27/10852 , H01L28/88 , H01L29/66181 , H01L2225/06541 , H01L2225/06551 , H01L2924/0002
摘要： Three-dimensional semiconductor structures are taught in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.
摘要翻译： 教导了三维半导体结构，其中各种器件类型由衬底上的多个平面层形成。 主要的工艺步骤包括形成多个交替的材料层，包括半导体和电介质材料，在层中形成垂直通孔，选择性地处理层以形成有源或无源半导体器件，以及用 导体。 最终结构包括三维存储器阵列，其中整个动态存储器单元以堆叠的垂直取向制造在形成在平面表面上的支撑电路上方。
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7.发明授权Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks 失效用于减少具有交替相移掩模的掩模偏置的分割虚拟填充形状的结构和方法公开(公告)号：US07709300B2
公开(公告)日：2010-05-04
申请号：US11539204
申请日：2006-10-06
IPC分类号： H01L21/82
CPC分类号： G06F17/5068 , G03F1/30 , G03F1/36 , G03F1/70 , G06F2217/12 , Y02P90/265
摘要： A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design that do not contain as-designed shapes. The method and system generates dummy fill shapes in the regions at a predetermined final density and sizes the generated dummy shapes so that their local density is increased to a predetermined value. The method and system further creates corresponding trim shapes that act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density. The method and system can be implemented on a computer program product comprising a computer useable medium including a computer readable program.
摘要翻译： 用于分割的虚拟填充形状的方法和系统，用于减少具有交替相移掩模的掩模偏置，或者使用采用修剪掩模的其它双掩模光刻工艺。 该方法和系统包括在完整的半导体设计中定位不具有设计形状的区域。 该方法和系统以预定的最终密度在区域中产生虚拟填充形状，并且对生成的虚拟形状进行尺寸化，使得它们的局部密度增加到预定值。 该方法和系统进一步产生相应的修剪形状，其用于暴露虚拟形状的超大部分，有效地将每个虚拟形状修剪回到预定的最终密度。 该方法和系统可以在包括包括计算机可读程序的计算机可用介质的计算机程序产品上实现。
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8.发明申请DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS 有权用于具有相移相位掩码的减少掩模偏差的分离式DUMMY FILL形状的设计结构公开(公告)号：US20090100399A1
公开(公告)日：2009-04-16
申请号：US11872924
申请日：2007-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density.
摘要翻译： 用于分割的虚拟填充形状的设计结构，方法和系统，用于减少具有交替相移掩模的掩模偏置，或者使用采用修剪掩模的其它双掩模光刻工艺。 设计结构体现在在设计过程中使用的机器可读介质中，该设计结构包括成品半导体设计中不包含设计形状的区域。 该设计结构还包括在预定最终密度的区域中的虚拟填充形状，其中所生成的虚拟形状的尺寸使得它们的局部密度增加到预定值。 此外，相应的修整形状用于暴露虚拟形状的超大部分，有效地将每个虚拟形状修剪回到预定的最终密度。
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公开(公告)号：US06287434B1
公开(公告)日：2001-09-11
申请号：US09460785
申请日：1999-12-14
IPC分类号： C25D1704
CPC分类号： C25D5/028 , Y10S204/07
摘要： A method and apparatus are provided for the electroplating on only one side of a substrate immersed in an electroplating bath using a device which holds the substrate to be plated in spaced relation to an inhibitor electrode of the device. To fabricate x-ray masks, a boron doped silicon substrate is secured to a dielectric clamp ring which clamp ring has a through opening which overlies the inhibitor electrode. A cathode structure overlies the clamp ring and the cathode structure, substrate and clamp ring are secured to the device by a pivotable, locking mechanism. A space is formed between the back side of the substrate and the surface of the inhibitor electrode so plating occurs on the surface of the inhibitor electrode. The substrate holding apparatus comprises a plate member to which the inhibitor electrode is secured. The clamp holding the substrate overlies the inhibitor electrode and a cathode structure is secured against the plate member.
摘要翻译： 提供了一种方法和装置，用于仅使用浸没在电镀浴中的基板的一侧进行电镀，该装置将待电镀的基板与装置的抑制电极间隔开。 为了制造x射线掩模，掺杂硼的硅衬底被固定到电介质夹环上，该夹环具有覆盖抑制电极的通孔。 阴极结构覆盖在夹紧环和阴极结构之间，衬底和夹环通过可枢转的锁定机构固定到装置上。 在基板的背面和抑制电极的表面之间形成空隙，从而在抑制电极的表面上发生电镀。 基板保持装置包括固定有抑制电极的板构件。 保持基板的夹具覆盖抑制电极，阴极结构固定在板件上。
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公开(公告)号：US6039858A
公开(公告)日：2000-03-21
申请号：US120774
申请日：1998-07-22
IPC分类号： C25D5/02
CPC分类号： C25D5/028 , Y10S204/07
摘要： A method and apparatus are provided for the electroplating on only one side of a substrate immersed in an electroplating bath comprising using a specially designed device which holds the substrate to be plated in spaced relation to an inhibitor electrode which is part of the device. To fabricate x-ray masks, a boron doped silicon substrate is secured to a dielectric clamp which clamp has a through opening which is positioned to overlie the inhibitor electrode. A cathode structure overlies the clamp and the cathode structure, substrate and clamp are secured to the device by preferably a pivotable, locking mechanism. A space is formed between the back side of the substrate and the surface of the inhibitor electrode so that plating is preferentially on the surface of the inhibitor electrode. The use of the method and apparatus minimizes plating on the backside of the substrate and provides a plated substrate on only the upper side of the substrate. The apparatus for holding the substrate comprises a plate member to which the inhibitor electrode is secured. The clamp holding the substrate is positioned overlying the inhibitor electrode and a cathode structure is secured against the plate member of the device and the assembled device is inserted in the electroplating bath for plating.
摘要翻译： 提供了一种方法和装置，用于仅在浸在电镀浴中的基板的一侧上进行电镀，其中包括使用专门设计的装置，其将待电镀基板与作为装置一部分的抑制电极间隔开。 为了制造X射线掩模，掺杂硼的硅衬底被固定到电介质夹具，夹具具有定位成覆盖抑制电极的通孔。 阴极结构覆盖在夹具和阴极结构之间，衬底和夹具优选地通过可枢转的锁定机构固定到装置上。 在基板的背面和抑制电极的表面之间形成空间，使得电镀优先在抑制电极的表面上。 使用该方法和装置使得在基板的背面上的电镀最小化，并且仅在基板的上侧提供镀覆的基板。 用于保持基板的装置包括固定有抑制电极的板构件。 保持基板的夹具定位在抑制器电极的上方，并且阴极结构固定在装置的板构件上，并且将组装的装置插入用于电镀的电镀浴中。
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