公开(公告)号：US06191016B1

公开(公告)日：2001-02-20

申请号：US09226503

申请日：1999-01-05

Applicant: Robert S. Chau ,  Thomas Letson ,  Patricia Stokley ,  Peter Charvat ,  Ralph Schweinfurth

Inventor： Robert S. Chau ,  Thomas Letson ,  Patricia Stokley ,  Peter Charvat ,  Ralph Schweinfurth

IPC: H01L213205

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  Y10S438/942 ,  Y10S438/945 ,  Y10S438/947 ,  Y10S438/95 ,  Y10S438/952

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract translation: 提供了一种结构，其包括半导体衬底，衬底上的栅极氧化物层和栅极氧化物层上的多晶硅层。 在多晶硅层上形成掩模层。 然后使用常规光刻技术将掩模层图案化成掩模，但不形成多晶硅层。 然后去除光致抗蚀剂层，然后将由掩模层图案化的掩模用于图案化多晶硅层。 当多晶硅层被图案化时，使用无碳掩模来构图多晶硅层而不是含有碳的常规光致抗蚀剂层导致较少的穿过栅极氧化物层的穿透。 通过栅极氧化物层的较少的突破允许使用更薄的栅极氧化物层，并且最终制造具有较低阈值电压的晶体管。

公开(公告)号：US20050241764A1

公开(公告)日：2005-11-03

申请号：US10838417

申请日：2004-05-03

Applicant: Thomas Letson ,  Don O'Neill

Inventor： Thomas Letson ,  Don O'Neill

IPC: C23F1/00 ,  H01L21/00

CPC classification number: H01L21/67069

Abstract: Systems and techniques for improving azimuthal symmetry in an etch process are described. In some implementations, a baffle may be used to modify the flow of gas in an etch process. A baffle may include a baffle wall, which may have at least two regions of equal radial extent. A first region may have a first open area percentage, while a fourth region may have a fourth open area percentage. The first open area percentage is smaller than the fourth open area percentage. The baffle may be positioned so that the first region is toward a vacuum inlet.

Abstract translation: 描述了用于改善蚀刻工艺中的方位对称性的系统和技术。 在一些实施方案中，挡板可用于在蚀刻工艺中改变气体流。 挡板可以包括挡板壁，其可以具有至少两个相等径向范围的区域。 第一区域可以具有第一开放区域百分比，而第四区域可以具有第四开放区域百分比。 第一个开放面积百分比小于第四个开放面积百分比。 挡板可以被定位成使得第一区域朝向真空入口。

公开(公告)号：US20070004123A1

公开(公告)日：2007-01-04

申请号：US11173660

申请日：2005-06-30

Applicant: Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

Inventor： Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

IPC: H01L21/8238

CPC classification number: H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract translation: 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US20060214231A1

公开(公告)日：2006-09-28

申请号：US11440313

申请日：2006-05-23

Applicant: Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

Inventor： Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20060086977A1

公开(公告)日：2006-04-27

申请号：US10973228

申请日：2004-10-25

Applicant: Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

Inventor： Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.