公开(公告)号：US08163605B2

公开(公告)日：2012-04-24

申请号：US12704004

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.

摘要翻译： 旨在提供一种能够获得用于降低源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及要获得的柱状半导体的期望直径的结构的SGT制造方法。 该方法包括以下步骤：形成柱状第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极电极的顶部接触的第一电介质膜，通过栅极电介质膜形成; 在所述栅电极的侧壁上形成第一电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层的上部和下方的每个第二导电型半导体层上形成金属 - 半导体化合物; 去除伪栅极电介质膜和伪栅电极并形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US20110303973A1

公开(公告)日：2011-12-15

申请号：US13116506

申请日：2011-05-26

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42392 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

摘要翻译： 根据本发明的半导体器件是nMOS SGT，并且由第一n +型硅层，含有金属的第一栅电极和第二n +型硅层构成，所述第二n +型硅层布置在垂直定位在第一n +型硅层上的第一柱状硅层的表面上 第一平面硅层。 此外，第一绝缘膜位于第一栅电极和第一平面硅层之间，第二绝缘膜位于第一栅电极的顶表面上。 此外，含有第一栅电极的金属被第一n +型硅层，第二n +型硅层，第一绝缘膜和第二绝缘膜包围。

公开(公告)号：US20100219464A1

公开(公告)日：2010-09-02

申请号：US12703991

申请日：2010-02-11

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/458 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在所述柱状的第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的叠层结构的栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成第一和第二侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属 - 半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成接触; 并且在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成接触。

公开(公告)号：US20100207199A1

公开(公告)日：2010-08-19

申请号：US12704000

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/66

CPC分类号： H01L29/78642 ,  H01L22/26

摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

公开(公告)号：US20100187600A1

公开(公告)日：2010-07-29

申请号：US12699611

申请日：2010-02-03

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US08519475B2

公开(公告)日：2013-08-27

申请号：US13289742

申请日：2011-11-04

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66666 ,  H01L29/78642

摘要： A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.

摘要翻译： 半导体器件包括形成在栅极电极和第一平坦半导体层之间的第一绝缘膜，以及侧壁形状的第二绝缘膜，其形成为围绕第一柱状硅层的上侧壁，同时接触栅电极的上表面和 以围绕栅电极和第一绝缘膜的侧壁。 半导体器件还包括形成在第一导电类型的第一半导体层的上表面上的第一半导体层的整体或上部形成的金属半导体化合物和第二半导体的上表面 形成在第一柱状半导体层的上部的第二导电类型的层。

公开(公告)号：US20130059423A1

公开(公告)日：2013-03-07

申请号：US13594022

申请日：2012-08-24

申请人： Tomohiko KUDO ,  Kiyonori OYU

发明人： Tomohiko KUDO ,  Kiyonori OYU

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： Provided is a method of manufacturing a semiconductor device, including: forming an active region surrounded by an element isolation region in a substrate; forming a pair of gate trenches in the active region; forming a pair of gate electrodes by embedding a conductor in the gate trenches; forming an implanted layer by implanting ions into a substrate surface between the gate electrodes; and thermally diffusing impurities of the implanted layer at least to a depth of bottom portions of the gate trenches by a transient enhanced diffusion method to form a diffusion layer region between the gate electrodes at least to a depth of bottom portions of the gate electrodes.

摘要翻译： 提供一种制造半导体器件的方法，包括：形成由衬底中的元件隔离区包围的有源区; 在有源区中形成一对栅极沟槽; 通过在栅极沟槽中嵌入导体来形成一对栅电极; 通过将离子注入到栅电极之间的衬底表面中来形成注入层; 以及通过瞬时增强扩散方法将所述注入层的杂质至少热沉扩散到所述栅极沟槽的底部的深度，以在所述栅电极之间至少至所述栅电极的底部的深度形成扩散层区域。

公开(公告)号：US20120299068A1

公开(公告)日：2012-11-29

申请号：US13478359

申请日：2012-05-23

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/78

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US20120142154A1

公开(公告)日：2012-06-07

申请号：US13354579

申请日：2012-01-20

申请人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.

摘要翻译： SGT制造方法包括形成柱状的第一导电型半导体层，在第一导电型半导体层的下方形成第二导电型半导体层。 在第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极，并且第一电介质膜形成在第一导电型半导体层的与顶部接触的第一导电型半导体层的侧壁的上部区域 栅电极。 第一电介质膜形成在栅电极的侧壁上，第二导电型半导体层形成在第一导电型半导体层的上部。 第二导电型半导体层形成在第一导电型半导体层的上部，并且在每个第二导电型半导体层上形成金属半导体化合物。 除去虚拟栅极电介质膜和虚拟栅电极，形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US06853037B2

公开(公告)日：2005-02-08

申请号：US09872007

申请日：2001-06-04

申请人： Tomohiko Kudo ,  Naohiko Kimizuka

发明人： Tomohiko Kudo ,  Naohiko Kimizuka

IPC分类号： H01L27/092 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/8238

摘要： A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p-types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.

摘要翻译： 半导体器件包括相对较低的阈值电平MOSFET和n型和p型相对较高的阈值级MOSFET。 较高阈值电平的MOSFET具有比下限阈值MOSFET厚的栅极氧化膜，此外，n型较高阈值电平MOSFET的栅极氧化膜比较高阈值电平MOSFET的栅极氧化膜厚 p型。 为了制造半导体器件，在栅氧化物处理之前进行氟离子的注入处理。 具体来说，对于n型和p型的较高阈值电平的MOSFET，独立的注入条件独立地进行氟离子的注入处理。