公开(公告)号：US08515374B2

公开(公告)日：2013-08-20

申请号：US13381608

申请日：2010-06-28

申请人： Toru Dan ,  Tomoyuki Tanabe ,  Haruo Kobayashi

发明人： Toru Dan ,  Tomoyuki Tanabe ,  Haruo Kobayashi

IPC分类号： H04B7/00

CPC分类号： H03L7/1075 ,  H03L7/099 ,  H03L7/101 ,  H03L2207/50

摘要： In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

摘要翻译： 在ADPLL电路中，基于在环路滤波器中设定了一定值的环路增益并基于数字控制振荡器的器件参数来估计的数字控制振荡器的增益时，DCO增益估计单元 估计在环路滤波器中设置另一个值的环路增益时数字控制振荡器的增益。

公开(公告)号：US08223058B2

公开(公告)日：2012-07-17

申请号：US12825744

申请日：2010-06-29

申请人： Shigeto Kobayashi ,  Atsushi Wada ,  Toru Dan

发明人： Shigeto Kobayashi ,  Atsushi Wada ,  Toru Dan

IPC分类号： H03M1/12

CPC分类号： H03M1/0607 ,  H01G4/38 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/167 ,  H03M1/802

摘要： A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.

摘要翻译： 电容器阵列电路接收多个输入信号，通过组合多个输入信号产生单个输出信号，并输出单个输出信号。 比较器接收电容器阵列电路的输出信号。 设置在预定的固定电压源和开关电容电路的输出端之间的电流源将电流提供给输出端，直到比较器的输出信号变化。 电容器阵列电路中的多个输入电容器彼此并行地接收多个输入信号。 电容器阵列电路中的至少一个附加的调节电容器存储电荷以补偿由比较器的延迟引起的偏移分量。 多个输入电容器和至少一个附加调节电容器的各个输出端子组合成一个。

公开(公告)号：US20120100821A1

公开(公告)日：2012-04-26

申请号：US13381608

申请日：2010-06-28

申请人： Toru Dan ,  Tomoyuki Tanabe ,  Haruo Kobayashi

发明人： Toru Dan ,  Tomoyuki Tanabe ,  Haruo Kobayashi

IPC分类号： H04B1/06 ,  H04B7/00 ,  H03L7/08

CPC分类号： H03L7/1075 ,  H03L7/099 ,  H03L7/101 ,  H03L2207/50

摘要： In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

摘要翻译： 在ADPLL电路中，基于在环路滤波器中设定了一定值的环路增益并基于数字控制振荡器的器件参数来估计的数字控制振荡器的增益时，DCO增益估计单元 估计在环路滤波器中设置另一个值的环路增益时数字控制振荡器的增益。

公开(公告)号：US07420833B2

公开(公告)日：2008-09-02

申请号：US10936593

申请日：2004-09-09

申请人： Toru Dan ,  Naofumi Sakai ,  Shigeharu Matsushita ,  Yoshiyuki Ishizuka

发明人： Toru Dan ,  Naofumi Sakai ,  Shigeharu Matsushita ,  Yoshiyuki Ishizuka

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

摘要翻译： 提供了能够抑制导致非选择存储单元中的数据消失的存储器。 该存储器包括存储单元阵列，其包括位线，与位线相交的字线和连接在位线和字线之间的存储单元，用于访问选定的存储单元，从而降低任意存储器中的剩余极化 然后在执行写入操作之后立即恢复所有存储器单元以恢复所有存储器单元以进行恢复，以在单次施加施加到访问中的非选择存储单元的电压之后执行剩余极化。

公开(公告)号：US20050068809A1

公开(公告)日：2005-03-31

申请号：US10936593

申请日：2004-09-09

申请人： Toru Dan ,  Naofumi Sakai ,  Shigeharu Matsushita ,  Yoshiyuki Ishizuka

发明人： Toru Dan ,  Naofumi Sakai ,  Shigeharu Matsushita ,  Yoshiyuki Ishizuka

IPC分类号： G11C7/02 ,  G11C11/22 ,  G11C16/06 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C11/22

摘要： A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

摘要翻译： 提供了能够抑制导致非选择存储单元中的数据消失的存储器。 该存储器包括存储单元阵列，其包括位线，与位线相交的字线和连接在位线和字线之间的存储单元，用于访问选定的存储单元，从而降低任意存储器中的剩余极化 然后在执行写入操作之后立即恢复所有存储器单元以恢复所有存储器单元以进行恢复，以在单次施加施加到访问中的非选择存储单元的电压之后执行剩余极化。

公开(公告)号：US20080297258A1

公开(公告)日：2008-12-04

申请号：US12153791

申请日：2008-05-23

申请人： Tomohiro Naito ,  Toru Dan

发明人： Tomohiro Naito ,  Toru Dan

IPC分类号： H03H11/10 ,  H03G5/10

CPC分类号： H03G1/007 ,  H03H11/245

摘要： A first transistor includes: a first terminal that receives one of differential input signals; a second terminal that receives a control signal for varying an impedance; a third terminal connected to the second transistor; and a fourth terminal that supplies a potential to a substrate. A second transistor includes: a fifth terminal that receives the other of the differential input signals; a sixth terminal that receives a control signal, the seventh terminal connected to the first transistor, and the eighth terminal that supplies a potential to a substrate. The third terminal, the fourth terminal, the seventh terminal, and the eighth terminal are connected together.

摘要翻译： 第一晶体管包括：第一端子，其接收差分输入信号之一; 接收用于改变阻抗的控制信号的第二终端; 连接到第二晶体管的第三端子; 以及向基板提供电位的第四端子。 第二晶体管包括：接收另一个差分输入信号的第五端子; 接收控制信号的第六端子，连接到第一晶体管的第七端子和向基板提供电位的第八端子。 第三端子，第四端子，第七端子和第八端子连接在一起。

公开(公告)号：US20100328119A1

公开(公告)日：2010-12-30

申请号：US12825744

申请日：2010-06-29

申请人： Shigeto Kobayashi ,  Atsushi Wada ,  Toru Dan

发明人： Shigeto Kobayashi ,  Atsushi Wada ,  Toru Dan

IPC分类号： H03M1/02 ,  H01G7/00

CPC分类号： H03M1/0607 ,  H01G4/38 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/167 ,  H03M1/802

摘要： A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.

摘要翻译： 电容器阵列电路接收多个输入信号，通过组合多个输入信号产生单个输出信号，并输出单个输出信号。 比较器接收电容器阵列电路的输出信号。 设置在预定的固定电压源和开关电容电路的输出端之间的电流源将电流提供给输出端，直到比较器的输出信号变化。 电容器阵列电路中的多个输入电容器彼此并行地接收多个输入信号。 电容器阵列电路中的至少一个附加的调节电容器存储电荷以补偿由比较器的延迟引起的偏移分量。 多个输入电容器和至少一个附加调节电容器的各个输出端子组合成一个。

公开(公告)号：US08866194B2

公开(公告)日：2014-10-21

申请号：US11902560

申请日：2007-09-24

申请人： Shinya Naito ,  Hideaki Fujiwara ,  Toru Dan

发明人： Shinya Naito ,  Hideaki Fujiwara ,  Toru Dan

IPC分类号： H01L29/66 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/737 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/78

摘要： A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.

摘要翻译： 半导体器件（npn双极晶体管）包括n型集电极层，由p +扩散层，SiGe层和p型硅膜构成的基极层，形成n型发射极层和电荷传输防止膜 在n型集电极层和n型发射极层之间，并且对于电子或空穴具有作为势垒的作用。

公开(公告)号：US08497733B2

公开(公告)日：2013-07-30

申请号：US13364488

申请日：2012-02-02

申请人： Nobuo Takahashi ,  Toru Dan ,  Masashi Aramomi ,  Yoshiyasu Kaneko

发明人： Nobuo Takahashi ,  Toru Dan ,  Masashi Aramomi ,  Yoshiyasu Kaneko

IPC分类号： H03F1/02

CPC分类号： H03F3/45475 ,  H03F3/45977 ,  H03F2203/45534

摘要： The present invention quickly detects an offset and prevents cutoff of low frequency signals. Offset detection circuits smooth an output of a variable gain amplifier at a predetermined time constant and detects the offset, which is a DC component. The detected offset is added to the input of the variable gain amplifier by an adder and the offset in the output of the variable gain amplifier is corrected. The time constant in the offset detection circuit is changed by the resistance values of the variable resistors. Then, the time constant is changed to a small time constant when the gain of the variable gain amplifier is changed and thereafter to a large time constant.

摘要翻译： 本发明快速检测偏移并防止低频信号的截止。 偏移检测电路以预定的时间常数平滑可变增益放大器的输出，并检测作为DC分量的偏移。 通过加法器将检测到的偏移量加到可变增益放大器的输入端，校正可变增益放大器输出端的偏移。 偏移检测电路中的时间常数由可变电阻器的电阻值改变。 然后，当可变增益放大器的增益改变并且之后到大的时间常数时，时间常数被改变为小的时间常数。

公开(公告)号：US20120200351A1

公开(公告)日：2012-08-09

申请号：US13364488

申请日：2012-02-02

申请人： Nobuo Takahashi ,  Toru Dan ,  Masashi Aramomi ,  Yoshiyasu Kaneko

发明人： Nobuo Takahashi ,  Toru Dan ,  Masashi Aramomi ,  Yoshiyasu Kaneko

IPC分类号： H03F1/34

CPC分类号： H03F3/45475 ,  H03F3/45977 ,  H03F2203/45534

摘要： The present invention quickly detects an offset and prevents cutoff of low frequency signals. Offset detection circuits smooth an output of a variable gain amplifier at a predetermined time constant and detects the offset, which is a DC component. The detected offset is added to the input of the variable gain amplifier by an adder and the offset in the output of the variable gain amplifier is corrected. The time constant in the offset detection circuit is changed by the resistance values of the variable resistors. Then, the time constant is changed to a small time constant when the gain of the variable gain amplifier is changed and thereafter to a large time constant.

摘要翻译： 本发明快速检测偏移并防止低频信号的截止。 偏移检测电路以预定的时间常数平滑可变增益放大器的输出，并检测作为DC分量的偏移。 通过加法器将检测到的偏移量加到可变增益放大器的输入端，校正可变增益放大器输出端的偏移。 偏移检测电路中的时间常数由可变电阻器的电阻值改变。 然后，当可变增益放大器的增益改变并且之后到大的时间常数时，时间常数被改变为小的时间常数。