公开(公告)号：US5973956A

公开(公告)日：1999-10-26

申请号：US509348

申请日：1995-07-31

申请人： Trevor Blyth ,  Richard T. Simko

发明人： Trevor Blyth ,  Richard T. Simko

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C27/005 ,  G11C7/16

摘要： Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state. A digital number can be represented by assigning a specific analog level to a digital number. The range of digital numbers that can be represented is determined by the analog voltage range divided by the accuracy to which the voltage may be stored and reliably retrieved. Other aspects and features of the invention are disclosed.

摘要翻译： 用于在非易失性存储器阵列中实现模拟存储的方法和装置。 该阵列由使用Fowler-Nordheim隧道擦除和热电子注入进行编程的存储器单元组成。 通过初始擦除执行写入单元格，随后是程序操作的受控序列，在该程序操作期间以小的增量对单元进行编程。 在每个程序步骤之后读取存储的电压，并且当从单元读回的电压相等或刚好超过所需的模拟电平时，程序步骤的顺序终止。 单元的读取条件将正电压施加到漏极或公共线，并向控制栅施加正电压。 源通过负载设备连接到负（地）电源。 单元格的输出是存在于源节点的实际电压。 没有电流检测或与参考电压进行比较以确定输出状态。 可以通过将特定模拟电平分配给数字号码来表示数字号码。 可以表示的数字数字的范围由模拟电压范围除以电压可以被存储和可靠地检索的精度决定。 公开了本发明的其它方面和特征。

公开(公告)号：US5294819A

公开(公告)日：1994-03-15

申请号：US981610

申请日：1992-11-25

申请人： Richard T. Simko

发明人： Richard T. Simko

IPC分类号： G11C16/04 ,  G11C27/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

CPC分类号： G11C16/0416 ,  G11C27/005 ,  H01L27/115 ,  H01L29/7883

摘要： The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array. Array operating voltages are chosen such that "program disturbance" is eliminated on cells adjacent to a cell undergoing programming. Finally, the present invention utilizes only a single polarity of operating voltages.

摘要翻译： 本发明公开了用于实现用于模拟或数字存储的单晶体管单元EEPROM阵列的方法和装置。 单晶体管存储单元可以通过在EEPROM存储晶体管的浮动栅极上连续地保持净负电荷来实现。 此外，根据本发明，通过在位于同一行的晶体管和位于相邻行中的晶体管之间共享公共扩散区，可以实现单晶体管单元的致密布局。 该公共扩散区域在擦除和编程模式中用作源，并在读取模式下用作漏极。 此外，本发明的共同扩散特征允许使用单个级别的金属将各种工作电压分配给EEPROM存储晶体管。 此外，利用单层金属允许简单且致密的制造，并且还减少了EEPROM存储阵列中的寄生电容。 选择阵列工作电压，使得在正在进行编程的单元相邻的单元上消除“程序干扰”。 最后，本发明仅使用单个极性的工作电压。

公开(公告)号：US5220531A

公开(公告)日：1993-06-15

申请号：US636879

申请日：1991-01-02

申请人： Trevor Blyth ,  Richard T. Simko

发明人： Trevor Blyth ,  Richard T. Simko

IPC分类号： G11C16/02 ,  G11C27/00

CPC分类号： G11C27/005

摘要： Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog recording and playback which provides increased resolution in the stored signal and increased accuracy and stability of the storage and readout capabilities of the device. The storage cell is configured wherein the electrically alterable MOS storage device is connected in a source follower configuration, which provides a one to one relationship between the variation in the floating gate storage charge and the variation in the output voltage, and for high load resistance, relative insensitivity to load characteristics. The write process and circuitry provides a multi iterative programming technique wherein a series of coarse pulses program a cell to the approximate desired value, with a series of fine pulses referenced to the last coarse pulse being used for programming the respective cell in fine increments to a desired final programming level. Still finer levels of programming can be used.

摘要翻译： 源跟随器存储单元以及用于集成电路模拟记录和重放的迭代写入的改进的方法和装置，其提供了存储信号中的增加的分辨率并且提高了设备​​的存储和读出能力的精度和稳定性。 存储单元被配置为其中可电可变MOS存储器件以源极跟随器配置连接，其提供浮置栅极存储电荷的变化和输出电压的变化之间的一对一关系，并且对于高负载电阻， 对负载特性的相对不敏感。 写入过程和电路提供了一种多重编程技术，其中一系列粗略脉冲将单元编程为近似的期望值，其中以最后一个粗略脉冲为基础的一系列精细脉冲以精细的增量编程到相应的单元 期望的最终编程水平。 可以使用更精细的编程水平。

公开(公告)号：US4520461A

公开(公告)日：1985-05-28

申请号：US367264

申请日：1982-04-12

申请人： Richard T. Simko

发明人： Richard T. Simko

IPC分类号： H01L27/112 ,  G11C5/14 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L23/522 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C5/147 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C5/145 ,  H01L23/522 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

公开(公告)号：US3996657A

公开(公告)日：1976-12-14

申请号：US648828

申请日：1976-01-13

申请人： Richard T. Simko ,  Phillip J. Salsbury

发明人： Richard T. Simko ,  Phillip J. Salsbury

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  B01J17/00

CPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/2253 ,  H01L21/28273 ,  H01L29/7836 ,  H01L29/7885

摘要： A double polycrystalline silicone gate memory device having a floating gate for storing charge and a control gate. The memory device may be used as a single device cell in a memory array. A double self-aligning method is used to form the source and drain regions while doping the gates. Through a predeposition step a lightly doped secondary source and drain regions are formed in alignment with the floating gate prior to the formation of the primary source and drain regions in alignment with the control gate.

摘要翻译： 一种具有用于存储电荷的浮动栅极和控制栅极的双晶多晶硅栅极存储器件。 存储器件可以用作存储器阵列中的单个器件单元。 使用双自对准方法在掺杂栅极时形成源区和漏区。 通过预沉积步骤，在形成与控制栅极对准的初级源极和漏极区域之前，形成与浮动栅极对准的轻掺杂次级源极和漏极区域。

公开(公告)号：US06961279B2

公开(公告)日：2005-11-01

申请号：US10798547

申请日：2004-03-10

申请人： Richard T. Simko

发明人： Richard T. Simko

IPC分类号： G11C16/10 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C14/00 ,  G11C14/0063 ,  G11C19/00 ,  G11C2216/10

摘要： A non-volatile memory element is operated, in part, in two phases. During the first phase, a voltage is applied to a first node coupled to the nonvolatile memory element to generate an initial voltage. During the second phase, a voltage is coupled through at least one capacitor to charge pump the initial voltage to a level sufficient for programming or erasing the non-volatile memory element.

摘要翻译： 非易失性存储元件部分地分两个阶段操作。 在第一阶段期间，将电压施加到耦合到非易失性存储元件的第一节点以产生初始电压。 在第二阶段期间，电压通过至少一个电容器耦合，以将初始电压充电到足以编程或擦除非易失性存储器元件的电平。

公开(公告)号：US4890259A

公开(公告)日：1989-12-26

申请号：US218634

申请日：1988-07-13

申请人： Richard T. Simko

发明人： Richard T. Simko

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  G11C27/02

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C27/005 ,  G11C27/024

摘要： The present invention is a high density integrated circuit analog signal recording and playback system. The recording and playback system is based upon an array storing analog signals. The array has rows and columns of non-volatile memory cells to store the signal information. Analog column read/write circuitry is used to both store the analog information and retrieve it on a real time basis, using interleaving of analog information on a plurality of sample/hold circuits prior to storage in the array to increase throughput.

摘要翻译： 本发明是高密度集成电路模拟信号记录和重放系统。 记录和播放系统基于存储模拟信号的阵列。 阵列具有用于存储信号信息的非易失性存储单元的行和列。 模拟列读/写电路用于存储模拟信息并且在存储在阵列之前在多个采样/保持电路上使用模拟信息的交错实时地检索模拟信息以提高吞吐量。

公开(公告)号：US4404475A

公开(公告)日：1983-09-13

申请号：US252231

申请日：1981-04-08

申请人： Joseph Drori ,  William H. Owen, III ,  Richard T. Simko

发明人： Joseph Drori ,  William H. Owen, III ,  Richard T. Simko

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/30 ,  H03K3/45 ,  H03K3/01 ,  H03L5/00

CPC分类号： G11C5/145 ,  G11C11/34 ,  G11C16/30

摘要： An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

摘要翻译： 一种用于产生调节的高电压隧道脉冲的集成电路系统，其电压电平随着电子穿过相应的第一和第二区域之间的一个或多个电介质间隙而引起的电压所需的电压电平变化。 将初始电子隧穿的电压电平与预定的电压余量进行比较，以使所述产生的隧穿电压脉冲的电压电平等于所检测的隧穿电压和所述电压余量之和。 然后在隧道脉冲放电之前，将隧道电压脉冲基本保持在该电平预定的持续时间。

公开(公告)号：US4326134A

公开(公告)日：1982-04-20

申请号：US71498

申请日：1979-08-31

申请人： William H. Owen ,  Richard T. Simko ,  Wallace E. Tchon

发明人： William H. Owen ,  Richard T. Simko ,  Wallace E. Tchon

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L27/02 ,  H02M7/25 ,  H02M9/06 ,  H03K4/02 ,  H03K5/02 ,  H03K5/12 ,  H03K3/57

CPC分类号： G11C16/30 ,  G11C5/145 ,  H01L27/0214 ,  H01L27/0218 ,  H03K4/02

摘要： Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

摘要翻译： 集成电路系统，用于利用由电容耦合的低电压时钟驱动的多个二极管连接级产生上升时间调节和电平控制的高电压脉冲。 最大输出电压可以由门控二极管参考器件控制，该器件提供与电源电压无关的参考电压。 可以提供反馈电路，其通过调制驱动高电压发生器的有效低电压时钟振幅来控制高电压上升时间。 还可以提供MOS逻辑电平接口电路用于感测达到预定的高电压电平。

公开(公告)号：US4300212A

公开(公告)日：1981-11-10

申请号：US6029

申请日：1979-01-24

申请人： Richard T. Simko

发明人： Richard T. Simko

IPC分类号： H01L27/112 ,  G11C5/14 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C14/00 ,  G11C16/0433 ,  H01L29/7883 ,  Y10S257/903

摘要： Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

摘要翻译： 非易失性半导体随机存取存储单元包括静态RAM单元和非易失性存储单元，其可以通过电容耦合与静态随机存取存储单元互连，使得RAM单元内容可以直接复制到非易失性元件，以及 使得在向RAM单元施加电力时非易失性存储单元的内容将被复制到RAM单元。 非易失性存储元件可以是结合有自调节和粗糙度增强的隧道电流的衬底耦合浮栅单元。