公开(公告)号：US20060189023A1

公开(公告)日：2006-08-24

申请号：US11064985

申请日：2005-02-23

申请人： Fa-Yuan Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai ,  Chau-Yang Wu

发明人： Fa-Yuan Chang ,  Hua-Shu Wu ,  Tsung-Mu Lai ,  Chau-Yang Wu

IPC分类号： H01L21/46

CPC分类号： B81C1/00047

摘要： A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an integrated circuit wafer with the cavities facing the integrated circuit wafer. The holder is removed to provide a first substrate with cavities formed therein facing the integrated circuit wafer and an insulator layer overlying the first substrate.

摘要翻译： 一种制造MEMS器件的方法，包括在其上提供具有绝缘体层的第一衬底。 保持器附接到绝缘体层，并且第一基板变薄。 此后，在第一基板中形成空腔，并将第一基板翻转并结合到集成电路晶片，其中空腔面向集成电路晶片。 保持器被移除以提供第一基板，其中形成有面向集成电路晶片的空腔和覆盖第一基板的绝缘体层。

公开(公告)号：US07732299B2

公开(公告)日：2010-06-08

申请号：US11673652

申请日：2007-02-12

申请人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiang Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Cheng ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

发明人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiang Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Cheng ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

IPC分类号： H01L21/338 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L23/585 ,  B81C1/0038 ,  B81C1/00611 ,  B81C2201/0125 ,  H01L21/31053 ,  H01L21/31056 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

摘要翻译： 本公开提供了一种制造微电子器件的方法。 该方法包括在第一衬底上形成顶部金属层，其中顶部金属层具有多个互连特征和第一虚拟特征; 在顶部金属层上形成第一介电层; 在与多个互连特征和顶部金属层的第一虚拟特征基本上垂直对准的目标区域中蚀刻第一介电层; 在第一介电层上进行化学机械抛光（CMP）工艺; 然后将第一基板接合到第二基板。

公开(公告)号：US20080194076A1

公开(公告)日：2008-08-14

申请号：US11673652

申请日：2007-02-12

申请人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiung Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Chang ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

发明人： Fa-Yuan Chang ,  Tsung-Mu Lai ,  Kai-Chih Liang ,  Hua-Shu Wu ,  Chin-Hsiung Ho ,  Gwo-Yuh Shiau ,  Chu-Wei Chang ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Chia-Shiung Tsai ,  Nick Y. M. Shen ,  Ching-Chung Pai

IPC分类号： H01L21/98

CPC分类号： H01L23/585 ,  B81C1/0038 ,  B81C1/00611 ,  B81C2201/0125 ,  H01L21/31053 ,  H01L21/31056 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

摘要翻译： 本公开提供了一种制造微电子器件的方法。 该方法包括在第一衬底上形成顶部金属层，其中顶部金属层具有多个互连特征和第一虚拟特征; 在顶部金属层上形成第一介电层; 在与多个互连特征和顶部金属层的第一虚拟特征基本上垂直对准的目标区域中蚀刻第一介电层; 在第一介电层上进行化学机械抛光（CMP）工艺; 然后将第一基板接合到第二基板。

公开(公告)号：US20080299769A1

公开(公告)日：2008-12-04

申请号：US11755437

申请日：2007-05-30

申请人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

发明人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

IPC分类号： H01L21/463

CPC分类号： B81C1/00634 ,  B81B2201/052

摘要： A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

摘要翻译： 一种方法包括在基底上方的第一区域中沉积牺牲材料层。 衬底的第一区域与衬底的第二区域分离，其中在第二区域上方设置耐腐蚀膜。 沉积耐腐蚀膜，使得耐腐蚀膜的第一部分在第一区域中的牺牲材料之上，并且耐腐蚀膜的第二部分高于第二区域。 通过化学机械抛光除去耐腐蚀膜的第一部分。 使用选择性蚀刻牺牲材料而不是耐腐蚀膜的蚀刻工艺从第一区域去除牺牲材料。

公开(公告)号：US08084361B2

公开(公告)日：2011-12-27

申请号：US11755437

申请日：2007-05-30

申请人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

发明人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

IPC分类号： H01L21/3213

CPC分类号： B81C1/00634 ,  B81B2201/052

摘要： A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

摘要翻译： 一种方法包括在基底上方的第一区域中沉积牺牲材料层。 衬底的第一区域与衬底的第二区域分离，其中在第二区域上方设置耐腐蚀膜。 沉积耐腐蚀膜，使得耐腐蚀膜的第一部分在第一区域中的牺牲材料之上，并且耐腐蚀膜的第二部分高于第二区域。 通过化学机械抛光除去耐腐蚀膜的第一部分。 使用选择性蚀刻牺牲材料而不是耐腐蚀膜的蚀刻工艺从第一区域去除牺牲材料。

公开(公告)号：US07696766B2

公开(公告)日：2010-04-13

申请号：US11731938

申请日：2007-04-02

申请人： Hsu Ming Cheng ,  Clinton Chao ,  Fa-Yuan Chang ,  Hua-Shu Wu

发明人： Hsu Ming Cheng ,  Clinton Chao ,  Fa-Yuan Chang ,  Hua-Shu Wu

IPC分类号： G01R31/02

CPC分类号： G01R1/07342 ,  G01R1/07378

摘要： A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.

摘要翻译： 提供一种测试半导体管芯的系统和方法。 一个实施例包括多个尖端，每个尖端包括具有导电通孔的衬底，具有连接到导电通孔的通孔的第一介电层，在第一介电层上方具有通孔的第二介电层以及第二介电层上的金属层 。 可以使用具有通孔的附加电介质层。 该尖端电连接到再分配线，其将尖端之间的信号路由到空间转换层上的电连接。 空间转换层使用例如诸如弹簧销的弹簧加载连接电连接到印刷电路板。 空间转换层通过一系列引导机构（如引导销或平滑的固定装置）对准印刷电路板，并通过调节螺丝来调整顶端的平面度。

公开(公告)号：US20080180123A1

公开(公告)日：2008-07-31

申请号：US11731938

申请日：2007-04-02

申请人： Hsu Ming Cheng ,  Clinton Chao ,  Fa-Yuan Chang ,  Hua-Shu Wu

发明人： Hsu Ming Cheng ,  Clinton Chao ,  Fa-Yuan Chang ,  Hua-Shu Wu

IPC分类号： G01R1/073 ,  G01R31/00

CPC分类号： G01R1/07342 ,  G01R1/07378

摘要： A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.

摘要翻译： 提供一种测试半导体管芯的系统和方法。 一个实施例包括多个尖端，每个尖端包括具有导电通孔的衬底，具有连接到导电通孔的通孔的第一介电层，在第一介电层上方具有通孔的第二介电层以及第二介电层上的金属层 。 可以使用具有通孔的附加电介质层。 该尖端电连接到再分配线，其将尖端之间的信号路由到空间转换层上的电连接。 空间转换层使用例如诸如弹簧销的弹簧加载连接电连接到印刷电路板。 空间转换层通过一系列引导机构（如引导销或平滑的固定装置）对准印刷电路板，并通过调节螺丝来调整顶端的平面度。

公开(公告)号：US20050029221A1

公开(公告)日：2005-02-10

申请号：US10637360

申请日：2003-08-09

申请人： Fa-Yuan Chang ,  Buh-Kuan Fang ,  Shih-Feng Chen ,  Cheng-Cheng Chang

发明人： Fa-Yuan Chang ,  Buh-Kuan Fang ,  Shih-Feng Chen ,  Cheng-Cheng Chang

IPC分类号： C23F1/00

CPC分类号： B81C1/00619

摘要： A process for etching deep trenches in a substrate for purposes such as the fabrication of microelectromechanical systems (MEMS), for example, on the substrate. The two-step process includes first etching a tapered trench having a tapered profile and enhanced sidewall passivation in a substrate along a protective mask which defines the desired trench profile on the substrate surface. Next, the tapered trench is trimmed by high-density plasma in an isotropic etching step to provide a straight-profile deep trench with minimum sidewall passivation.

摘要翻译： 用于蚀刻基板中的深沟槽的方法，例如在基板上制造微机电系统（MEMS）。 两步工艺包括首先沿着保护掩模在衬底中蚀刻具有锥形轮廓和增强的侧壁钝化的锥形沟槽，所述保护掩模在衬底表面上限定所需的沟槽轮廓。 接下来，在各向同性蚀刻步骤中通过高密度等离子体修剪锥形沟槽，以提供具有最小侧壁钝化的直轮廓深沟槽。

公开(公告)号：US6069091A

公开(公告)日：2000-05-30

申请号：US999205

申请日：1997-12-29

申请人： Fa-Yuan Chang ,  Ming-Yeon Hung

发明人： Fa-Yuan Chang ,  Ming-Yeon Hung

IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/76224

摘要： A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing hard mask layer, where the blanket silicon containing hard mask layer is formed from a silicon containing material chosen from the group of silicon containing materials consisting of silicon oxide materials, silicon nitride materials, silicon oxynitride materials and composites of silicon oxide materials, silicon nitride materials and silicon oxynitride materials. There is then formed upon the blanket silicon containing hard mask layer a patterned photoresist layer. There is then etched through a first plasma etch method the blanket silicon containing hard mask layer to form a patterned silicon containing hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorine and carbon containing etchant source gas and a first bromine containing etchant source gas. Finally, there is then etched in-situ through a second plasma etch method the blanket silicon layer to form an at least partially etched silicon layer while employing the patterned photoresist layer and the patterned silicon containing hard mask layer as a second etch mask. The second plasma etch method employs a second etchant gas composition comprising a second fluorine and carbon containing etchant source gas, a second bromine containing etchant source gas and a chlorine containing etchant source gas.

摘要翻译： 一种在微电子制造中蚀刻硅层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成覆盖硅层。 然后在橡皮布硅层上形成含有覆盖硅的硬掩模层，其中，含硅的硬掩模层由含硅材料形成，所述含硅材料选自由硅氧化物材料，氮化硅材料， 氮氧化硅材料和氧化硅材料，氮化硅材料和氮氧化硅材料的复合材料。 然后在橡皮布含硅的硬掩模层上形成图案化的光致抗蚀剂层。 然后通过第一等离子体蚀刻方法蚀刻包含硅的硬掩模层，以形成图案化的含硅硬掩模层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层。 第一等离子体蚀刻方法采用包含第一含氟和碳的蚀刻剂源气体和第一含溴腐蚀剂源气体的第一蚀刻剂气体组合物。 最后，然后通过第二等离子体蚀刻方法将橡皮布硅层原位蚀刻以形成至少部分蚀刻的硅层，同时使用图案化的光致抗蚀剂层和图案化的含硅硬掩模层作为第二蚀刻掩模。 第二等离子体蚀刻方法采用包含第二含氟和碳的蚀刻剂源气体的第二蚀刻剂气体组合物，第二含溴蚀刻剂源气体和含氯腐蚀剂源气体。

公开(公告)号：US06679064B2

公开(公告)日：2004-01-20

申请号：US10144521

申请日：2002-05-13

申请人： Chih-Wei Chang ,  Fa-Yuan Chang ,  Cheng-Ting Tseng ,  Chin-Chang Chen ,  Cheng-Cheng Chang ,  Shih-Fang Chen

发明人： Chih-Wei Chang ,  Fa-Yuan Chang ,  Cheng-Ting Tseng ,  Chin-Chang Chen ,  Cheng-Cheng Chang ,  Shih-Fang Chen

IPC分类号： F25B2102

CPC分类号： H01L35/32 ,  F25B21/04 ,  F25B2321/021

摘要： A wafer transfer system having a temperature control apparatus. The temperature control apparatus is constructed and arranged so that a material, element, or atomic particle may flow therethrough to heat or cool a wafer carried by the wafer transfer system. The material, element or atomic particle flowing through the temperature control apparatus causes heat to be pumped to or from an upper surface or lower surface. Preferably the temperature control apparatus is a thermoelectric device. Preferably the thermoelectric device includes a plurality of alternating N-type and P-type semiconductor pellets arranged electrically in series and thermally in parallel, and connected to a DC power supply. A switch or relay is provided for altering the direction of current flow to the thermoelectric device from a DC supply.

摘要翻译： 一种具有温度控制装置的晶片传送系统。 温度控制装置被构造和布置成使得材料，元素或原子粒子可以流过其中以加热或冷却由晶片传送系统承载的晶片。 流过温度控制装置的材料，元素或原子粒子使得热量被泵送到上表面或下表面。 优选地，温度控制装置是热电装置。 优选地，热电装置包括多个交替的N型和P型半导体芯片，其电串联并联并联并且并联连接到DC电源。 提供开关或继电器，用于从直流电源改变到热电装置的电流的方向。