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51 条记录 (耗时 0.035 秒)

    Semiconductor integrated circuit
    1.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07412616B2

    公开(公告)日：2008-08-12

    申请号：US10895394

    申请日：2004-07-21

    申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    IPC分类号： H04L7/00

    CPC分类号： G06F13/4243 ,  G06F13/1689

    摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

    摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07945801B2

    公开(公告)日：2011-05-17

    申请号：US12169853

    申请日：2008-07-09

    申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    IPC分类号： H04L7/00

    CPC分类号： G06F13/4243 ,  G06F13/1689

    摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

    摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20080276112A1

    公开(公告)日：2008-11-06

    申请号：US12169853

    申请日：2008-07-09

    申请人： SHIGEZUMI MATSUI ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    发明人： SHIGEZUMI MATSUI ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

    IPC分类号： H04L7/00

    CPC分类号： G06F13/4243 ,  G06F13/1689

    摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

    摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。