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36 条记录 (耗时 0.036 秒)

    Techniques for controlling on-chip termination resistance using voltage range detection
    1.
    发明授权
    Techniques for controlling on-chip termination resistance using voltage range detection 有权
    使用电压范围检测控制片上终端电阻的技术

    公开(公告)号：US07218155B1

    公开(公告)日：2007-05-15

    申请号：US11040343

    申请日：2005-01-20

    申请人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    发明人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0005

    摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

    摘要翻译： 提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 校准电路监视外部电阻和片上晶体管组之间的电压。 当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。 校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

    DLL with adjustable phase shift using processed control signal
    2.
    发明授权
    DLL with adjustable phase shift using processed control signal 有权
    具有可调相移的DLL使用处理后的控制信号

    公开(公告)号：US07212054B1

    公开(公告)日：2007-05-01

    申请号：US11479660

    申请日：2006-06-29

    申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

    发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0805

    摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

    摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。

    DLL with adjustable phase shift using processed control signal
    3.
    发明授权
    DLL with adjustable phase shift using processed control signal 有权
    具有可调相移的DLL使用处理后的控制信号

    公开(公告)号：US07091760B1

    公开(公告)日：2006-08-15

    申请号：US10788221

    申请日：2004-02-25

    申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

    发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0805

    摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

    摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。

    Clock edge de-skew
    4.
    发明授权
    Clock edge de-skew 有权
    时钟边缘去偏移

    公开(公告)号：US07590879B1

    公开(公告)日：2009-09-15

    申请号：US11043524

    申请日：2005-01-24

    申请人： Henry Kim ,  Bonnie I. Wang ,  ChiaKang Sung ,  Joseph Huang

    发明人： Henry Kim ,  Bonnie I. Wang ,  ChiaKang Sung ,  Joseph Huang

    IPC分类号： G06F1/12 ,  G06F9/00 ,  G06F13/42

    CPC分类号： G06F13/4243

    摘要： Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.

    摘要翻译： 用于对时钟信号的上升沿和下降沿进行偏移的电路，方法和装置。 本发明的一个实施例利用数据路径中的延迟元件来调整数据信号，使得时钟信号相对于数据居中。 本发明的另一实施例使用两个触发器来恢复双数据速率信号，其中一个触发器由时钟上升沿计时，另一个由时钟下降沿计时。 在一个或两个触发器时钟输入的前面插入一个附加的延迟元件。 如果使用两个额外的延迟元件，则它们可独立调节，以便可以独立调整每个边沿以改善数据恢复。

    Apparatus and method for controlling a delay chain
    5.
    发明授权
    Apparatus and method for controlling a delay chain 有权
    用于控制延迟链的装置和方法

    公开(公告)号：US07205802B1

    公开(公告)日：2007-04-17

    申请号：US11349516

    申请日：2006-02-03

    申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

    发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

    IPC分类号： H03L7/06

    CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

    摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

    摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

    Apparatus and method for controlling a delay chain
    6.
    发明授权
    Apparatus and method for controlling a delay chain 失效
    用于控制延迟链的装置和方法

    公开(公告)号：US07030675B1

    公开(公告)日：2006-04-18

    申请号：US10932642

    申请日：2004-08-31

    申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

    发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

    IPC分类号： H03H11/26

    CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

    摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

    摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

    Bone plate with bladed portion
    8.
    发明授权
    Bone plate with bladed portion 有权
    骨板与叶片部分

    公开(公告)号：US07229445B2

    公开(公告)日：2007-06-12

    申请号：US10874097

    申请日：2004-06-21

    申请人： Garry Hayeck ,  René Haag ,  Henry Kim ,  Mark P. Grady, Jr.

    发明人： Garry Hayeck ,  René Haag ,  Henry Kim ,  Mark P. Grady, Jr.

    IPC分类号： A61B17/80

    CPC分类号： A61B17/74 ,  A61B17/8014 ,  A61B17/8057 ,  A61B17/809

    摘要： A bone plate for fixation of a fractured bone includes a first portion having a first longitudinal axis and a second portion having a second longitudinal axis. The second portion is angled with respect to the first portion. The first portion has at least one hole for receiving a bone anchor having a shaft. The hole has a first hole portion defining a first central axis substantially perpendicular to a lower surface of the first portion and configured to receive the bone anchor. The hole includes a second hole portion overlapping and in communication with the first hole portion from upper to lower surface defining a second central axis substantially angled with respect to the first central axis, and configured to receive the bone anchor such that the shaft is substantially angled with respect to the second portion of the bone plate so as to form a truss.

    摘要翻译： 用于固定骨折骨的骨板包括具有第一纵向轴线的第一部分和具有第二纵向轴线的第二部分。 第二部分相对于第一部分成角度。 第一部分具有用于接收具有轴的骨锚的至少一个孔。 孔具有限定基本上垂直于第一部分的下表面的第一中心轴线的第一孔部分，并且构造成容纳骨锚。 所述孔包括第二孔部分，其重叠并且与第一孔部分从上到下表面连通，限定相对于第一中心轴线基本成角度的第二中心轴线，并且构造成接收骨锚，使得轴基本成角度 相对于骨板的第二部分形成桁架。

    Method for soldering and desoldering electronic components
    10.
    发明授权
    Method for soldering and desoldering electronic components 失效
    焊接和拆焊电子部件的方法

    公开(公告)号：US4771932A

    公开(公告)日：1988-09-20

    申请号：US95637

    申请日：1987-09-14

    申请人： Henry Kim

    发明人： Henry Kim

    IPC分类号： B23K3/02 ,  H05K3/34 ,  B23K31/02

    CPC分类号： B23K3/026 ,  B23K3/025 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/3494

    摘要： A soldering iron which is developed specifically to address a wide variety of miniaturized integrated circuit soldered pin configurations has a handle with a heating block which mounts one of a set of wide, chisel-shaped blades that are engaged in a deep channel in the heating block and which taper gradually to a knife edge which is the operative edge of the soldering head. The wide, thin, extensively tapered and knife-edged blade usually addresses a row of integrated circuit pins or surface mounted leads to act brush-like to solder them substantially at the same time, or to heat them substantially simultaneously when desoldering the row to remove the component.

    摘要翻译： 专门用于解决各种小型化集成电路焊接引脚配置的烙铁具有带有加热块的手柄，该加热块安装了一组宽的凿形刀片中的一个，其接合在加热块中的深通道中 并且其逐渐变细到作为焊接头的操作边缘的刀刃。 宽，薄，宽的锥形和刀刃通常地处理一排集成电路引脚或表面安装的引线，以实质上同时刷刷以焊接它们，或者当拆焊行以去除时基本上同时加热它们 组件。