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    Vertical cavity surface emitting laser diode (VCSEL) having AlGaAsP layer with compressive strain
    1.
    发明授权
    Vertical cavity surface emitting laser diode (VCSEL) having AlGaAsP layer with compressive strain 有权

    公开(公告)号：US11721954B2

    公开(公告)日：2023-08-08

    申请号：US16931541

    申请日：2020-07-17

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Chao-Hsing Huang ,  Yu-Chung Chin ,  Van-Truong Dai

    IPC: H01S5/34 ,  H01S5/183

    CPC classification number: H01S5/3403 ,  H01S5/18361

    Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with low compressive strain DBR layer, including a GaAs substrate, a lower DBR layer, a lower spacer layer, an active region, an upper spacer layer and an upper DBR layer. The lower or the upper DBR layer includes multiple low refractive index layers and multiple high refractive index layers. The lower DBR layer, the lower spacer layer, the upper spacer layer or the upper DBR layer contains AlxGa1-xAs1-yPy, where the lattice constant of AlxGa1-xAs1-yPy is greater than that of the GaAs substrate. This can moderately reduce excessive compressive strain due to lattice mismatch or avoid tensile strain during the epitaxial growth, thereby reducing the chance of deformation and bowing of the VCSEL epitaxial wafer or cracking during manufacturing. Additionally, the VCSEL epitaxial layer can be prevented from generating excessive compressive strain or tensile strain during the epitaxial growth.

    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) WITH SMALL DIVERGENCE ANGLE
    2.
    发明申请
    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) WITH SMALL DIVERGENCE ANGLE 有权

    公开(公告)号：US20230121340A1

    公开(公告)日：2023-04-20

    申请号：US17966544

    申请日：2022-10-14

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Van-Truoung Dai ,  Yu-Chung Chin ,  Chao-Hsing Huang

    IPC: H01S5/183

    Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with a small divergence angle. The VCSEL includes a multi-layer structure on a substrate. The multi-layer structure includes an active region and current confinement layers. Each of the current confinement layers has an optical aperture (OA). When the area of the OA of the current confinement layer outside the active region is larger than the areas of the OAs of the current confinement layers inside the active region, such that the VCSEL has a small divergence angle in the short pulse mode.

    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) WITH TUNNEL JUNCTION
    3.
    发明申请
    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) WITH TUNNEL JUNCTION 有权

    公开(公告)号：US20210104872A1

    公开(公告)日：2021-04-08

    申请号：US17060287

    申请日：2020-10-01

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Chao-Hsing Huang ,  Yu-Chung Chin ,  Van-Truong Dai

    IPC: H01S5/30 ,  H01S5/183 ,  H01S5/02 ,  H01S5/343

    Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL). A tunnel junction with a high doping concentration is provided in the VCSEL. An n-type semiconductor layer of the tunnel junction has stress relative to the substrate, and is doped with at least one element such that the tunnel junction not only has a high doping concentration, but also the epitaxial layer can be oxidized and the oxidation rate is relatively stable during the oxidation process. Alternatively, the n-type semiconductor layer is doped with at least two elements. As a result, the oxidation process of the VCSEL can be stably performed, and the resistance of the tunnel junction with a high doping concentration is low. The tunnel junction is suitable to be arranged between two active layers of the VCSEL or between the p-type semiconductor and the n-type semiconductor layer of the VCSEL.

    HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR
    4.
    发明申请
    HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR 审中-公开
    高电子移动双极晶体管

    公开(公告)号：US20140361344A1

    公开(公告)日：2014-12-11

    申请号：US14326673

    申请日：2014-07-09

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang

    IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20

    CPC classification number: H01L29/778 ,  H01L29/0821 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7371 ,  H01L29/7378 ,  H01L29/7785

    Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm−3 and 1×1020 cm−3, and/or the oxygen concentration within 5×1018 cm−3 and 1×1020 cm−3.The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

    Abstract translation: 公开了一种高电子迁移率双极晶体管，其包括从底部到顶部顺序层叠的基板，伪晶体高电子迁移率晶体管（pHEMT）子结构，子集电极/分离层和异质结双极晶体管（HBT）子结构。 将亚集电极/分离层和pHEMT子结构组合形成pHEMT，并将亚集电极/分离层和HBT子结构组合形成HBT。 子集电极/分离层中的碳浓度在5×1017cm-3和1×1020cm-3之间，和/或氧浓度在5×1018cm-3和1×1020cm-3之间。 在外延生长过程中的晶格是稳定的，并且可以防止掺杂剂，元素，空位或缺陷扩散到相邻层中，从而改善迁移率降低和电阻增加的问题，并且保持稳定性 制造过程。

    HIGH-POWER VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL)
    6.
    发明申请
    HIGH-POWER VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) 有权

    公开(公告)号：US20210091537A1

    公开(公告)日：2021-03-25

    申请号：US17029177

    申请日：2020-09-23

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Chao-Hsing Huang ,  Yu-Chung Chin ,  Van-Truong Dai

    IPC: H01S5/183

    Abstract: Provided is a high-power vertical cavity surface emitting laser diode (VCSEL), including a first epitaxial region, an active region and a second epitaxial region. One of the first epitaxial region and the second epitaxial region is an N-type epitaxial region, and the other of the first epitaxial region and the second epitaxial region includes a PN junction. The PN junction includes a P-type epitaxial layer, a tunnel junction and an N-type epitaxial layer. The tunnel junction is located between the P-type epitaxial layer and the N-type epitaxial layer, and the P-type epitaxial layer of the PN junction is closest to the active region.

    HIGH RUGGEDNESS HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE
    7.
    发明申请
    HIGH RUGGEDNESS HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE 审中-公开

    公开(公告)号：US20200161421A1

    公开(公告)日：2020-05-21

    申请号：US16292365

    申请日：2019-03-05

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang ,  Min-Nan Tseng ,  Kai-Yu Chen

    IPC: H01L29/08 ,  H01L33/00 ,  H01L29/737 ,  H01L29/205

    Abstract: The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of AlxGa1-xAs, AlxGa1-xAs1-yNy, AlxGa1-xAs1-zPz, AlxGa1-xAs1-wSbw, and InrAlxGa1-x-rAs, x having a highest value between 0.05≤x≤0.4, and y, z, r, w≤0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.

    SEMICONDUCTOR COMPONENT HAVING DEFECT BARRIER REGION
    9.
    发明公开
    SEMICONDUCTOR COMPONENT HAVING DEFECT BARRIER REGION 审中-公开

    公开(公告)号：US20240079510A1

    公开(公告)日：2024-03-07

    申请号：US18143991

    申请日：2023-05-05

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Van-Truong DAI ,  Yu-Chung CHIN ,  Chao-Hsing HUANG

    IPC: H01L31/0352 ,  H01L31/0304

    CPC classification number: H01L31/035236 ,  H01L31/0304

    Abstract: The present invention is a semiconductor device having a defect blocking region. The semiconductor device includes a substrate, a defect source region, a semiconductor layer and a defect blocking region. The defect source region is on the substrate, wherein the defect source region is a metamorphic buffer layer or a buffer layer, the semiconductor layer over the defect source region, wherein a lattice constant of the semiconductor layer is different from a lattice constant of the substrate. The defect blocking region is disposed on the substrate and below the semiconductor layer, wherein the defect blocking region includes a superlattice structure, wherein at least one of two adjacent layers of the superlattice structure has strain relative to the semiconductor layer, or a lattice constant of the superlattice structure is close to or equal to the lattice constant of the semiconductor layer.

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