公开(公告)号：US20140120722A1

公开(公告)日：2014-05-01

申请号：US13981974

申请日：2012-01-26

申请人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

发明人： Thomas B. Richardson ,  Joseph A. Abys ,  Wenbo Shao ,  Chen Wang ,  Vincent Paneccasio, JR. ,  Cai Wang ,  Xuan Lin ,  Theodore Antonellis

IPC分类号： H01L21/768

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76898

摘要： A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

摘要翻译： 一种用于在半导体集成电路器件中通过硅通孔特征进行金属化的工艺，该过程包括在填充周期期间使电路的极性反转一段间隔以在所述金属化衬底处产生阳极电位，并从铜表面解吸整齐器 通孔，然后通过重新建立通孔内的铜的表面作为电路中的阴极来恢复铜沉积，由此产生铜填充的通孔特征。

公开(公告)号：US20130199935A1

公开(公告)日：2013-08-08

申请号：US13699910

申请日：2011-05-24

申请人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

发明人： Thomas B. Richardson ,  Wenbo Shao ,  Xuan Lin ,  Cai Wang ,  Vincent Paneccasio, JR. ,  Joseph A. Abys ,  Yun Zhang ,  Richard Hurtubise ,  Chen Wang

IPC分类号： C25D3/38

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76898

摘要： A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

摘要翻译： 一种用于在半导体集成电路器件衬底中金属化硅通孔特征的方法。 该方法包括将半导体集成电路器件衬底浸入电解铜沉积组合物中，其中贯穿硅通孔特征具有介于1微米至100微米之间的入口尺寸，20微米至750微米的深度尺寸，以及大于 约2：1; 向电解沉积组合物供给电流以将铜金属沉积到底部和侧壁上以进行自底向上填充，由此产生铜填充的通孔特征。 沉积组合物包含（a）铜离子源; （b）选自无机酸，有机磺酸及其混合物的酸; （c）有机二硫化物; （d）选自苄基氯和羟乙基亚乙基亚胺的反应产物，季铵化吡啶基化合物及其组合的化合物; 和（d）氯离子。

公开(公告)号：US20100126872A1

公开(公告)日：2010-05-27

申请号：US12324335

申请日：2008-11-26

申请人： Vincent Paneccasio, JR. ,  Xuan Lin ,  Richard Hurtubise ,  Qingyun Chen

发明人： Vincent Paneccasio, JR. ,  Xuan Lin ,  Richard Hurtubise ,  Qingyun Chen

IPC分类号： C25D7/12 ,  C25D3/38

CPC分类号： H01L21/76879 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

摘要翻译： 一种用于金属化半导体集成电路器件衬底中的通孔特征的方法，其中所述半导体集成电路器件衬底包括前表面，后表面和所述通孔特征，并且其中所述通孔特征包括在所述衬底的前表面中的开口 ，从基板的前表面向内延伸的侧壁和底部。 该方法包括使半导体集成电路器件衬底与包含（a）铜离子源和（b）整平剂化合物的电解铜沉积化学物质接触，其中矫光剂化合物是二吡啶基化合物和烷基化剂的反应产物; 并向电解沉积化学物质提供电流以将铜金属沉积到通孔特征的底部和侧壁上，从而产生铜填充的通孔特征。

公开(公告)号：US07615491B2

公开(公告)日：2009-11-10

申请号：US11243876

申请日：2005-10-05

申请人： Qingyun Chen ,  Charles Valverde ,  Vincent Paneccasio ,  Nicolai Petrov ,  Daniel Stritch ,  Christian Witt ,  Richard Hurtubise

发明人： Qingyun Chen ,  Charles Valverde ,  Vincent Paneccasio ,  Nicolai Petrov ,  Daniel Stritch ,  Christian Witt ,  Richard Hurtubise

IPC分类号： H01L21/44

CPC分类号： C09D5/10 ,  C23C18/34 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

公开(公告)号：US20070289875A1

公开(公告)日：2007-12-20

申请号：US11846385

申请日：2007-08-28

申请人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

发明人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

IPC分类号： C25D3/38

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/12 ,  C25D7/123 ,  H01L21/76877

摘要： An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

摘要翻译： 一种用于在具有亚微米尺寸互连特征的半导体集成电路基板上电解电镀Cu的电解电镀方法和组合物。 该组合物包含Cu离子源和包含聚醚基团的抑制剂化合物。 该方法包括以超填充速度的快速自下而上沉积来超填充，通过其从特征的底部到特征的顶部开口的垂直方向上的Cu沉积基本上大于侧壁上的Cu沉积。

公开(公告)号：US20070066058A1

公开(公告)日：2007-03-22

申请号：US11243624

申请日：2005-10-05

申请人： Qingyun Chen ,  Charles Valverde ,  Vincent Paneccasio ,  Nicolai Petrov ,  Daniel Stritch ,  Christian Witt ,  Richard Hurtubise

发明人： Qingyun Chen ,  Charles Valverde ,  Vincent Paneccasio ,  Nicolai Petrov ,  Daniel Stritch ,  Christian Witt ,  Richard Hurtubise

IPC分类号： H01L23/58 ,  H01L21/44 ,  H01L21/31 ,  H01L23/48

CPC分类号： C09D5/10 ,  C23C18/34 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

公开(公告)号：US07998859B2

公开(公告)日：2011-08-16

申请号：US12238139

申请日：2008-09-25

申请人： Qingyun Chen ,  Xuan Lin ,  Vincent Paneccasio, Jr. ,  Richard Hurtubise ,  Joseph A. Abys

发明人： Qingyun Chen ,  Xuan Lin ,  Vincent Paneccasio, Jr. ,  Richard Hurtubise ,  Joseph A. Abys

IPC分类号： H01L21/00

CPC分类号： H01L21/76873 ,  H01L21/02068 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76861 ,  H01L21/76874

摘要： A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.

摘要翻译： 公开了一种用于金属化包括在微电子器件的制造中的互连特征的衬底的方法，其中所述互连特征包括底部，侧壁和具有直径D的顶部开口。该方法包括以下步骤： 所述阻挡层包括选自由钌，钨，钽，钛，铱，铑及其组合组成的组的金属; 使包含所述底部和侧壁的所述基底的所述基底与所述阻挡层接触，所述水性组合物包含还原剂和表面活性剂; 以及在其上具有阻挡层的互连部件的底部和侧壁上沉积铜金属。

公开(公告)号：US20100075496A1

公开(公告)日：2010-03-25

申请号：US12238139

申请日：2008-09-25

申请人： Qingyun Chen ,  Xuan Lin ,  Vincent Paneccasio, JR. ,  Richard Hurtubise

发明人： Qingyun Chen ,  Xuan Lin ,  Vincent Paneccasio, JR. ,  Richard Hurtubise

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  H01L21/02068 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76861 ,  H01L21/76874

摘要： A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.

摘要翻译： 公开了一种用于金属化包括在微电子器件的制造中的互连特征的衬底的方法，其中所述互连特征包括底部，侧壁和具有直径D的顶部开口。该方法包括以下步骤： 所述阻挡层包括选自由钌，钨，钽，钛，铱，铑及其组合组成的组的金属; 使包含所述底部和侧壁的所述基底的所述基底与所述阻挡层接触，所述水性组合物包含还原剂和表面活性剂; 以及在其上具有阻挡层的互连部件的底部和侧壁上沉积铜金属。

公开(公告)号：US07332193B2

公开(公告)日：2008-02-19

申请号：US11085304

申请日：2005-03-21

申请人： Charles Valverde ,  Nicolai Petrov ,  Eric Yakobson ,  Qingyun Chen ,  Vincent Paneccasio, Jr. ,  Richard Hurtubise ,  Christian Witt

发明人： Charles Valverde ,  Nicolai Petrov ,  Eric Yakobson ,  Qingyun Chen ,  Vincent Paneccasio, Jr. ,  Richard Hurtubise ,  Christian Witt

IPC分类号： C23C18/16 ,  C23C18/36 ,  C23C18/32

CPC分类号： H01L21/76849 ,  C23C18/34 ,  C23C18/36 ,  C23C18/50 ,  H01L21/288 ,  H05K3/244

摘要： An electroless plating method and composition for depositing Co, Ni, or alloys thereof onto a metal-based substrate in manufacture of microelectronic devices, involving a source of deposition ions selected from the group consisting of Co ions and Ni ions, a reducing agent for reducing the depositions ions to metal onto the substrate, and a hydrazine-based leveling agent.

摘要翻译： 一种用于在制造微电子器件时将Co，Ni或其合金沉积在金属基底上的化学镀方法和组合物，其包括选自Co离子和Ni离子的沉积离子源，用于还原的还原剂 沉积到金属到基底上的离子，以及基于肼的流平剂。

公开(公告)号：US20070178697A1

公开(公告)日：2007-08-02

申请号：US11346459

申请日：2006-02-02

申请人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise ,  Christian Witt

发明人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise ,  Christian Witt

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/123 ,  H01L21/76877

摘要： An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is greater than Cu deposition on the side walls.

摘要翻译： 一种用于在具有亚微米尺寸互连特征的半导体集成电路基板上电解电镀Cu的电解电镀方法和组合物。 该组合物包含Cu离子源和包含聚醚基团的抑制剂化合物。 该方法包括以超填充速度的快速自下而上的沉积，通过其从特征的底部到特征的顶部开口的垂直方向上的Cu沉积大于侧壁上的Cu沉积。