公开(公告)号：US4536738A

公开(公告)日：1985-08-20

申请号：US460501

申请日：1983-01-24

申请人： Horst Huse ,  Werner Elmer

发明人： Horst Huse ,  Werner Elmer

IPC分类号： H03K19/173 ,  G06F7/04

CPC分类号： H03K19/1733

摘要： A programmable circuit arrangement is described which can be programmed by applying a programming voltage so that it delivers at its output a signal having a predetermined binary value. The circuit arrangement comprises an input means responsive to the programming voltage. Further, it comprises a conducting means connected to the input means and capable of being brought to a non-conductive state upon application of the programming voltage to the input means. The circuit arrangement further comprises an output means connected to the conductive means and delivering a signal having one binary value in the conductive state of the conductive means and the other binary value in the non-conductive state of the conductive means.

摘要翻译： 描述了可编程电路装置，其可以通过施加编程电压进行编程，使得其在其输出端输出具有预定二进制值的信号。 电路装置包括响应编程电压的输入装置。 此外，它包括连接到输入装置的导电装置，并且当将编程电压施加到输入装置时能够使其处于非导通状态。 电路装置还包括连接到导电装置的输出装置，并且在导电装置的导通状态下传送具有导通状态的一个二进制值的信号，并且在导电装置的非导通状态下传送另一个二进制值。

公开(公告)号：US07436238B2

公开(公告)日：2008-10-14

申请号：US11673847

申请日：2007-02-12

申请人： Horst Jungert ,  Werner Elmer

发明人： Horst Jungert ,  Werner Elmer

IPC分类号： H03K17/00

CPC分类号： H03K17/693 ,  H03K17/005 ,  H03K19/1732

摘要： An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

摘要翻译： 可以在工作模式之间切换集成电路，而不需要专用模式选择引脚。 用于在指定的最大电源电压下操作的电路包括第一和第二电源端子，用于施加常规输入信号的第一信号输入端，第二信号输入端和输出端。 该电路还包括多路复用器，其具有分别连接到第一和第二信号输入的第一和第二输入，用于在选择信号的控制下选择性地将第一和第二信号输入中的任一个切换到输出。 门电路向多路复用器提供选择信号。 门电路的输入由控制电路驱动。 提供了限制多路复用器第一个输入端的电压的钳位电路。 通过这样的电路设计，施加到第一信号输入端的相对较高的电压将将电路切换到另一操作模式，例如测试模式。

公开(公告)号：US4920283A

公开(公告)日：1990-04-24

申请号：US272157

申请日：1988-11-16

申请人： Werner Elmer ,  Michael Schmitt

发明人： Werner Elmer ,  Michael Schmitt

IPC分类号： H01L21/8222 ,  H01L27/06 ,  H03K17/16 ,  H03K17/62 ,  H03K19/003 ,  H03K19/018

CPC分类号： H03K19/00353 ,  H03K17/16

摘要： An integrated circuit is described which includes a plurality of output transistors (T1, T2, . . . Tn) for emitting binary signals to associated output terminals (A1, A2, . . . An). The integrated circuit further includes at least one ground terminal (M; M1, M2 . . . Mn). Between the base of each transistor (T1, T2, . . . Tn) and the at least one ground terminal (M; M1, M2, . . . Mn) a current source (R1, D1) controlled by the base voltage is inserted.

摘要翻译： 描述了一种集成电路，其包括用于向相关联的输出端子（A1，A2，...）发射二进制信号的多个输出晶体管（T1，T2 ... Tn）。 集成电路还包括至少一个接地端子（M; M1，M2 ... Mn）。 在每个晶体管的基极（T1，T2 ... Tn）和至少一个接地端子（M; M1，M2 ... Mn）之间插入由基极电压控制的电流源（R1，D1） 。

公开(公告)号：US4740919A

公开(公告)日：1988-04-26

申请号：US846329

申请日：1986-03-31

申请人： Werner Elmer

发明人： Werner Elmer

IPC分类号： H03K19/177 ,  G01R31/3185 ,  G11C29/52 ,  G11C11/40

CPC分类号： G01R31/318516 ,  G11C29/52

摘要： An electrically programmable logic array (10) for binary signals having signal inputs A.sub.0 -A.sub.x) and signal outputs Q.sub.0 -Q.sub.i) comprises two row lines (a.sub.0,a.sub.0' -a.sub.x, a.sub.x') for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q.sub.0 -q.sub.i) is provided.In the non-programmable state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S.sub.0,S.sub.0',-S.sub.x, S.sub.x') which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

摘要翻译： 对于每个信号输入，具有用于具有信号输入A0-Ax）和信号输出Q0-Qi的二进制信号的电可编程逻辑阵列（10））包括两条行线（a0，a0'-ax，ax'）。 施加到信号输入端的信号可以在一个行中以非负形式和另一行以负数形式生成。 对于每个信号输出，提供列线（q0-qi）。 在每个行线和每条列线之间的非可编程状态下，存在可编程的导电连接。 插入到信号输入和每个相关联的行线之间的连接中的是可控开关元件（S0，S0'，-Sx，Sx'），其可以通过施加到其上的控制信号控制，使得其输出信号随着 施加到相关联的信号输入或与所述信号无关的信号总是保持预定的信号值。

公开(公告)号：US20070205821A1

公开(公告)日：2007-09-06

申请号：US11673847

申请日：2007-02-12

申请人： Horst JUNGERT ,  Werner ELMER

发明人： Horst JUNGERT ,  Werner ELMER

IPC分类号： H03K17/00

CPC分类号： H03K17/693 ,  H03K17/005 ,  H03K19/1732

摘要： An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. The control circuitry detects a voltage at the first signal input that exceeds the specified maximum supply voltage by a given amount and, in response, applies a drive signal to the input of the gate circuit. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

摘要翻译： 可以在工作模式之间切换集成电路，而不需要专用模式选择引脚。 用于在指定的最大电源电压下操作的电路包括第一和第二电源端子，用于施加常规输入信号的第一信号输入端，第二信号输入端和输出端。 该电路还包括多路复用器，其具有分别连接到第一和第二信号输入的第一和第二输入，用于在选择信号的控制下选择性地将第一和第二信号输入中的任一个切换到输出。 门电路向多路复用器提供选择信号。 门电路的输入由控制电路驱动。 提供了限制多路复用器第一个输入端的电压的钳位电路。 控制电路将第一信号输入端的电压检测到超过指定的最大电源电压一定给定的量，并且作为响应，向门电路的输入端施加驱动信号。 通过这样的电路设计，施加到第一信号输入端的相对较高的电压将将电路切换到另一操作模式，例如测试模式。

公开(公告)号：US5488288A

公开(公告)日：1996-01-30

申请号：US974869

申请日：1992-11-12

申请人： Werner Elmer

发明人： Werner Elmer

IPC分类号： H01L23/58 ,  G05F1/46 ,  G05F1/567 ,  H01L21/8249 ,  H01L27/06 ,  H03K17/04 ,  H03K17/14 ,  H03K17/60 ,  H03K17/687 ,  H03K19/003

CPC分类号： G05F1/567 ,  G05F1/462 ,  Y10S323/907

摘要： The present invention relates to a circuit arrangement integrated in a semiconductor circuit. In modern microprocessor systems with high clock rates (50 MHz and more) special chips with narrow tolerance ranges as regards their switching speed are required. The circuit arrangement according to the invention compensates the switching speed fluctuations due to temperature fluctuations and process spread by generating an internal operating voltage and controlling said voltage in such a manner that it counteracts the fluctuations of the switching speed due to temperature changes and process spread and compensates said fluctuations.

摘要翻译： 本发明涉及集成在半导体电路中的电路装置。 在具有高时钟频率（50MHz及更高​​）的现代微处理器系统中，需要具有关于其切换速度的窄公差范围的专用芯片。 根据本发明的电路装置通过产生内部工作电压来补偿由于温度波动和过程扩展引起的开关速度波动，并且以这样的方式控制所述电压，使得其抵消由于温度变化和过程传播引起的开关速度的波动， 补偿所述波动。

公开(公告)号：US5374858A

公开(公告)日：1994-12-20

申请号：US134513

申请日：1993-10-08

申请人： Werner Elmer

发明人： Werner Elmer

IPC分类号： G06F3/00 ,  G06F13/40 ,  H03K17/14 ,  H03K19/003 ,  H03K19/018 ,  H03K17/60

CPC分类号： H03K19/01806 ,  G06F13/4072 ,  H03K19/00376

摘要： A bus driver circuit for applying a binary signal to a bus line comprises an input transistor (Q.sub.1) for receiving the signal to be applied to the bus line and an output transistor (Q.sub.2) which taps the signal from the emitter of the input transistor and furnishes its output signal at its collector via a Schottky diode (D.sub.1). Between the base and the collector of the output transistor (Q.sub.2) the collector-emitter path of a transistor (Q.sub.3) is inserted, to the base of which a reference voltage (U.sub.ref) for defining the low value (L) of the binary signal to be applied to the bus line is applied via a Schottky diode (D.sub.3).

摘要翻译： 用于将二进制信号施加到总线的总线驱动器电路包括用于接收要施加到总线线路的信号的输入晶体管（Q1）和从输入晶体管的发射极触发信号的输出晶体管（Q2），以及 通过肖特基二极管（D1）在其集电极处提供其输出信号。 在输出晶体管（Q2）的基极和集电极之间插入晶体管（Q3）的集电极 - 发射极路径，其基极用于定义二进制信号的低值（L）的参考电压（Uref） 通过肖特基二极管（D3）施加到总线上。