公开(公告)号：US5751932A

公开(公告)日：1998-05-12

申请号：US485217

申请日：1995-06-07

申请人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

发明人： Robert W. Horst ,  William Edward Baker ,  Randall G. Banton ,  John Michael Brown ,  William F. Bruckert ,  William Patterson Bunton ,  Gary F. Campbell ,  John Deane Coddington ,  Richard W. Cutts, Jr. ,  Barry Lee Drexler ,  Harry Frank Elrod ,  Daniel L. Fowler ,  David J. Garcia ,  Paul N. Hintikka ,  Geoffrey I. Iswandhi ,  Douglas Eugene Jewett ,  Curtis Willard Jones, Jr. ,  James Stevens Klecka ,  John C. Krause ,  Stephen G. Low ,  Susan Stone Meredith ,  Steven C. Meyers ,  David P. Sonnier ,  William Joel Watson ,  Patricia L. Whiteside ,  Frank A. Williams ,  Linda Ellen Zalzala

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 CPU被构造为以两种模式之一操作：两个CPU彼此独立地操作的单工模式，以及CPU以锁步同步操作的双工模式，以基本上执行相同指令流的每条指令 同一时间。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US06233702B1

公开(公告)日：2001-05-15

申请号：US08485055

申请日：1995-06-07

申请人： Robert W. Horst ,  David J. Garcia ,  William Patterson Bunton ,  William F. Bruckert ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  David Paul Sonnier ,  William Joel Watson ,  Frank A. Williams

发明人： Robert W. Horst ,  David J. Garcia ,  William Patterson Bunton ,  William F. Bruckert ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  David Paul Sonnier ,  William Joel Watson ,  Frank A. Williams

IPC分类号： G06F1100

CPC分类号： G01R31/31727 ,  G01R31/318533 ,  G06F1/12 ,  G06F11/004 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F12/0815 ,  G06F12/1483 ,  G06F2201/845 ,  H04L12/56 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信.I / O设备和CPU之间的通信是通过分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息包.CPU和I / O设备可以写入或读取来自CPU的CPU的存储器 系统。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5751955A

公开(公告)日：1998-05-12

申请号：US473541

申请日：1995-06-07

申请人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  John C. Krause ,  Michael P. Simpson ,  William Joel Watson

发明人： David Paul Sonnier ,  William Edward Baker ,  William Patterson Bunton ,  Daniel L. Fowler ,  Curtis Willard Jones, Jr. ,  John C. Krause ,  Michael P. Simpson ,  William Joel Watson

IPC分类号： G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14

CPC分类号： G01R31/31727 ,  G06F1/12 ,  G06F11/10 ,  G06F11/1604 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/40 ,  G01R31/318533 ,  G06F11/004 ,  G06F11/1044 ,  G06F11/167 ,  G06F11/1683 ,  G06F11/1695 ,  G06F11/20 ,  G06F11/2043 ,  G06F11/2097 ,  G06F11/2736 ,  G06F2201/845 ,  H04L12/56

摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

摘要翻译： 多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。 任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。 来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。 存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

公开(公告)号：US5316654A

公开(公告)日：1994-05-31

申请号：US776179

申请日：1985-09-13

申请人： Donald C. Berkebile, deceased ,  Catherine Berkebile, Administratrix ,  Donald M. Lee ,  Larry D. Veneziano ,  Joseph J. Lauer ,  Roy E. Booth ,  William P. Hettinger ,  Willard Jones

发明人： Donald C. Berkebile, deceased ,  Catherine Berkebile, Administratrix ,  Donald M. Lee ,  Larry D. Veneziano ,  Joseph J. Lauer ,  Roy E. Booth ,  William P. Hettinger ,  Willard Jones

IPC分类号： C10C3/00 ,  C10C1/00

CPC分类号： C10C3/00

摘要： There are provided improved processes for the manufacture of enriched pitches, carbon fiber precursors, carbon fibers, and graphite fibers. The improvement comprises employing an elevated wiped-film evaporator in a wiped-film evaporator system comprising the wiped-film evaporator and a means for recovering enriched pitch, such as a positive displacement pump, to form an enriched pitch from catalytic pitch and regulating the operating conditions of the wiped-film evaporator system to provide the desired enriched pitch. The wiped-film evaporator is located a specific distance above the means for recovering enriched pitch. The vertical distance between the outlet of the wiped-film evaporator and the inlet of the means for recovering enriched pitch is within the range of about 10 feet to about 40 feet, preferably about 20 feet to about 40 feet.

摘要翻译： 提供了用于制造富集沥青，碳纤维前体，碳纤维和石墨纤维的改进方法。 该改进包括在包括刮膜蒸发器的擦拭膜蒸发器系统中采用升高的擦拭膜蒸发器和用于回收富集沥青的装置，例如正位移泵，以从催化沥青形成富集的沥青并调节操作 擦拭膜蒸发器系统的条件以提供所需的富集沥青。 擦拭膜蒸发器位于用于回收富集沥青的装置上方的特定距离处。 擦拭膜蒸发器的出口和用于回收富集沥青的装置的入口之间的垂直距离在约10英尺至约40英尺的范围内，优选约20英尺至约40英尺。

公开(公告)号：US5136746A

公开(公告)日：1992-08-11

申请号：US731243

申请日：1991-07-17

申请人： Willard Jones

发明人： Willard Jones

IPC分类号： A43D3/02

CPC分类号： A43D3/025

摘要： A universal shoe holder having a detachable mounting member for securing the holder to a work surface, and a supporting member which supports the shoe holding mechanism perpendicular to the mounting member. The shoe holding mechanism consists of a holding member fastened to the support member, and a heel support member which is pivotally attached thereto. A tightening mechanism is provided which exerts pressure on the heel support member and the holding member, allowing the shoe holder to securely hold various styles and sizes of shoes during repair and polishing procedures. An adjusting mechanism is included to allow the shoe holder to be adjusted to fit different sizes of shoes.

摘要翻译： 具有用于将保持件固定到工作表面的可拆卸安装构件的通用鞋架，以及支撑构件，其支撑垂直于安装构件的鞋保持机构。 鞋保持机构由固定在支撑件上的保持件和可枢转地连接到其上的跟部支承件构成。 提供了一种紧固机构，其对脚跟支撑构件和保持构件施加压力，从而允许鞋保持器在修理和抛光过程期间可靠地保持各种款式和尺寸的鞋。 包括调节机构，以允许鞋保持器被调整以适合不同尺寸的鞋。