公开(公告)号：US06274915B1

公开(公告)日：2001-08-14

申请号：US09225646

申请日：1999-01-05

申请人： Srinath Krishnan ,  Ming-Yin Hao ,  David Bang ,  Witold Maszara

发明人： Srinath Krishnan ,  Ming-Yin Hao ,  David Bang ,  Witold Maszara

IPC分类号： H01L2976

CPC分类号： H01L29/4916 ,  H01L29/1033

摘要： A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1×1019 and 5×1019 atoms/cm3.

摘要翻译： MOS晶体管的设计故意使用多晶硅栅电极中的耗尽来改善电路性能。 常规的晶体管设计旨在最小化多晶硅栅电极的耗尽以增加驱动电流。 根据本发明的实施例，大于常规电平的栅电极的适当耗尽量同时提供期望的驱动电流同时最小化电路延迟。 根据另一方面，通过调整沟道区域中的掺杂水平来改善电路性能，以将阈值电压维持在与多晶硅栅电极中的最小耗尽所达到的阈值电压相同的水平。 还提供了一种制造包括具有增加的耗尽的多晶硅栅电极的MOS器件的方法。 使用自对准掺杂工艺，其中多晶硅栅极，源极区域和漏极区域被同时注入到掺杂剂浓度为1×1019至5×1019原子/ cm3之间。

公开(公告)号：US08933567B2

公开(公告)日：2015-01-13

申请号：US12784706

申请日：2010-05-21

申请人： David Bang ,  Thomas Andrew Myers

发明人： David Bang ,  Thomas Andrew Myers

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

摘要翻译： 半导体管芯具有围绕半导体管芯的周围布置的多个不连续的导电段，以及在导电段之间的不连续部分内的电绝缘阻挡层。 导电段和阻挡层围绕半导体管芯形成机械连续的密封环。

公开(公告)号：US20090261433A1

公开(公告)日：2009-10-22

申请号：US12355911

申请日：2009-01-19

申请人： Seung H. Kang ,  David Bang ,  Kangho Lee

发明人： Seung H. Kang ,  David Bang ,  Kangho Lee

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

摘要翻译： 将磁性隧道结（MTJ）器件集成到集成电路中的方法包括在半导体后端（BEOL）工艺流程中提供具有第一层间介电层和至少第一金属互连的衬底。 在第一层间介电层和第一金属互连之后，沉积磁隧道结材料层。 从材料层，使用单个掩模工艺来限定耦合到第一金属互连的磁性隧道结叠层。 磁性隧道结堆叠集成在集成电路中。

公开(公告)号：US06268277B1

公开(公告)日：2001-07-31

申请号：US09356029

申请日：1999-07-16

申请人： David Bang

发明人： David Bang

IPC分类号： H01L214763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The method involves forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric region, forming an air gap at least partially within the dielectric region, and sealing the air gap to entrap the air gap between the first and second metal regions thereby reducing intralevel capacitance between the first and second metal regions.

摘要翻译： 一种降低镶嵌金属化过程中的体积电容的方法在金属线之间使用夹带的气隙。 该方法包括使用镶嵌工艺形成金属化图案，其包括至少形成由电介质区分开的第一和第二金属区域，至少部分地在电介质区域内形成气隙，并密封气隙以截留 第一和第二金属区域从而降低第一和第二金属区域之间的电容。

公开(公告)号：US08483997B2

公开(公告)日：2013-07-09

申请号：US12493110

申请日：2009-06-26

申请人： Xia Li ,  Wei Zhao ,  David Bang ,  Yu Cao ,  Seung H. Kang ,  Matthew Nowak

发明人： Xia Li ,  Wei Zhao ,  David Bang ,  Yu Cao ,  Seung H. Kang ,  Matthew Nowak

IPC分类号： G06F7/60

CPC分类号： G06F17/5036

摘要： A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.

摘要翻译： 计算机程序产品估计半导体集成电路（IC）的后端（BEOL）结构的性能。 代码在计算机上执行，以基于特定于BEOL结构的多个层的输入数据来动态地预测BEOL结构的电阻。 BEOL结构可以是一个触点或通孔。 接触/通孔的层包括内部填充材料和外部衬垫。 该代码考虑了内部填充材料的宽度散射效应，以及接触/通孔的斜率分布。

公开(公告)号：US06047243A

公开(公告)日：2000-04-04

申请号：US989079

申请日：1997-12-11

申请人： David Bang ,  Qi Xiang

发明人： David Bang ,  Qi Xiang

IPC分类号： G01R31/12 ,  G01R27/02

CPC分类号： G01R31/129

摘要： An ultra-thin dielectric film is subject to a dynamic electrical bias. During a first phase, the ultra-thin dielectric film is under a high field bias generated by the application of a high voltage. The duration of the high electrical stress is dependent on the intrinsic properties of the ultra-thin dielectric material. In a second phase, the ultra-thin dielectric film is subjected to an operating field bias generated by the application of an operating voltage. The change in the field bias exposes the dielectric to a similar dynamic stress that microelectronic devices ordinarily experience. At the operating field stage, a gate current is measured and compared to a predetermined range. Once the gate current exceeds that range the test concludes. Otherwise, the test cycles between the above-mentioned phases for a predetermined number of iterations based on prior experimental correlation. In a destructive testing mode, the process is continuous and does not conclude until the gate current exceeds a predetermined range. The ultra-thin dielectric gate current may also be measured as the ultra-thin dielectric is heated so that the transport properties or reliability of the ultra-thin dielectric is more clearly understood.

摘要翻译： 超薄介电膜受到动态电偏压。 在第一阶段期间，超薄介电膜处于通过施加高电压产生的高场偏压下。 高电应力的持续时间取决于超薄介电材料的固有特性。 在第二阶段中，超薄电介质膜受到通过施加工作电压而产生的工作场偏压。 场偏置的变化将电介质暴露于微电子器件通常经历的类似动态应力。 在操作场阶段，测量栅极电流并将其与预定范围进行比较。 一旦栅极电流超过该范围，测试就会结束。 否则，基于先前的实验相关性，测试在上述阶段之间进行预定次数的迭代。 在破坏性测试模式中，该过程是连续的，并且在栅极电流超过预定范围之前不能得出结论。 当超薄电介质被加热时，也可以测量超薄电介质栅极电流，以便更清楚地了解超薄电介质的传输特性或可靠性。

公开(公告)号：US5953625A

公开(公告)日：1999-09-14

申请号：US990270

申请日：1997-12-15

申请人： David Bang

发明人： David Bang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002

摘要： A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

摘要翻译： 提供了一种用于在多电平VLSI半导体集成电路器件中制造金属线的方法，以便减少寄生电容。 执行底切蚀刻步骤，以在金属线下方形成用于容纳空气空隙的沟槽，随后在金属线之间形成层内电介质并进入沟槽中，以在金属线下方形成空气空隙。 结果，寄生电容将减小。

公开(公告)号：US09159910B2

公开(公告)日：2015-10-13

申请号：US12355911

申请日：2009-01-19

申请人： Seung H. Kang ,  David Bang ,  Kangho Lee

发明人： Seung H. Kang ,  David Bang ,  Kangho Lee

IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

摘要翻译： 将磁性隧道结（MTJ）器件集成到集成电路中的方法包括在半导体后端（BEOL）工艺流程中提供具有第一层间介电层和至少第一金属互连的衬底。 在第一层间介电层和第一金属互连之后，沉积磁隧道结材料层。 从材料层，使用单个掩模工艺来限定耦合到第一金属互连的磁性隧道结叠层。 磁性隧道结堆叠集成在集成电路中。

公开(公告)号：US08207569B2

公开(公告)日：2012-06-26

申请号：US11758763

申请日：2007-06-06

申请人： David Bang

发明人： David Bang

IPC分类号： H01L27/107

CPC分类号： H01G4/06 ,  H01G4/38 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/43 ,  H01L2924/00

摘要： Capacitive structures in integrated circuits are disclosed. The capacitive structures are formed on a substrate. Each capacitive structure includes a first conductive finger and a second conductive finger. The first and second conductive fingers are arranged in parallel with each other and separated from each other by a dielectric material. The first finger is connected to a first interconnect and the second conductive finger is connected to a second interconnect. A first capacitor is formed from a first group of the plurality of capacitive structures having respective interconnects coupled together. A second capacitor is formed from a second group of the plurality of capacitive structures having respective interconnects coupled together. The capacitive structures of the first group are intertwined with the capacitive structures of the second group.

摘要翻译： 公开了集成电路中的电容结构。 电容结构形成在基板上。 每个电容结构包括第一导电手指和第二导电手指。 第一和第二导电指状物彼此平行地布置并且通过电介质材料彼此分离。 第一手指连接到第一互连，第二导电指连接到第二互连。 第一电容器由多个电容结构的第一组形成，具有耦合在一起的各自的互连。 第二电容器由具有耦合在一起的相应互连的多个电容结构的第二组形成。 第一组的电容结构与第二组的电容结构相互缠绕。

公开(公告)号：US6127193A

公开(公告)日：2000-10-03

申请号：US80917

申请日：1998-05-18

申请人： David Bang ,  Takeshi Nogami ,  Guarionex Morales ,  Shekhar Pramanick

发明人： David Bang ,  Takeshi Nogami ,  Guarionex Morales ,  Shekhar Pramanick

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  H01L2924/0002

摘要： A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.