公开(公告)号：US08026589B1

公开(公告)日：2011-09-27

申请号：US12390999

申请日：2009-02-23

Applicant: Bong Chan Kim ,  Do Hyung Kim ,  Chan Ha Hwang ,  Min Woo Lee ,  Eun Sook Sohn ,  Won Joon Kang

Inventor： Bong Chan Kim ,  Do Hyung Kim ,  Chan Ha Hwang ,  Min Woo Lee ,  Eun Sook Sohn ,  Won Joon Kang

IPC: H01L23/48

CPC classification number: H01L24/48 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49517 ,  H01L24/16 ,  H01L24/29 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/85001 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove. In this instance, conductive material layers may be disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires, with solder pads further bring electrically connected to respective ones of the conductive material layers and at least partially residing within the groove.

Abstract translation: 根据本发明，提供了缩减轮廓可堆叠半导体封装的多个实施例。 半导体封装包括具有至少一个连接到其上的半导体管芯的衬底。 半导体管芯也通过多个导电线电连接到衬底。 限定相对的顶表面和底表面的封装主体和至少部分地封装基板，导线和半导体管芯的侧表面。 封装体形成为使得导线的至少一部分在其顶表面中露出。 封装体可以包括形成在其顶表面中的凹槽，其中至少一部分导电线暴露在凹槽中。 在这种情况下，导电材料层可以设置在凹槽内并且电连接到相应的导电线的暴露部分，焊料垫进一步电连接到相应的导电材料层，并且至少部分地位于 槽。