公开(公告)号：US08456212B2

公开(公告)日：2013-06-04

申请号：US13050652

申请日：2011-03-17

申请人： Woo-Seok Kim ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

发明人： Woo-Seok Kim ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

摘要翻译： 一个占空比校正电路包括占空比转子电路，差分时钟发生器和电荷泵电路。 占空比电路响应于占空比控制信号校正输入时钟信号的占空比，并产生输出时钟信号。 差分时钟发生器基于输出时钟信号产生彼此相位差为180°的两个内部时钟信号。 电荷泵电路响应于内部时钟信号在差分模式下执行电荷泵操作以产生占空比控制信号。

公开(公告)号：US08361274B2

公开(公告)日：2013-01-29

申请号：US11032651

申请日：2005-01-10

申请人： Kwang-Myung Lee ,  Ki-Young Yun ,  Il-Kyoung Kim ,  Sung-Wook Park ,  Seung-Ki Chae ,  No-Hyun Huh ,  Jae-Wook Kim ,  Jae-Hyuck An ,  Woo-Seok Kim ,  Myeong-Jin Kim ,  Kyoung-Ho Jang ,  Shinji Yanagisawa ,  Kengo Tsutsumi ,  Seiichi Takahashi

发明人： Kwang-Myung Lee ,  Ki-Young Yun ,  Il-Kyoung Kim ,  Sung-Wook Park ,  Seung-Ki Chae ,  No-Hyun Huh ,  Jae-Wook Kim ,  Jae-Hyuck An ,  Woo-Seok Kim ,  Myeong-Jin Kim ,  Kyoung-Ho Jang ,  Shinji Yanagisawa ,  Kengo Tsutsumi ,  Seiichi Takahashi

IPC分类号： H01L21/3065 ,  C23C16/455 ,  C23C16/00

CPC分类号： H01L21/6708 ,  H01J37/3244 ,  H01L21/3065

摘要： A vacuum processing apparatus is provided with: a vacuum processing tank; a first gas introduction section that is constructed such that a first processing gas in a radical state is introduced into the vacuum processing tank and is guided to a semiconductor wafer; and a second gas introduction section that is constructed such that a second processing gas that reacts with the first processing gas is introduced into the vacuum processing tank and is guided to the semiconductor wafer. The second gas introduction section has two shower nozzles provided at positions on either side of an introduction pipe provided for the first gas introduction section. According to this vacuum processing apparatus, high speed processing of a number of processing objects can be achieved. Moreover, the in-plane uniformity of the processing objects after processing can be ensured.

摘要翻译： 真空处理装置具有：真空处理槽; 第一气体导入部，被构造成使得自由基状态的第一处理气体被引入到真空处理槽中并被引导到半导体晶片; 以及第二气体导入部，其被构造成使得与第一处理气体反应的第二处理气体被引入到真空处理槽中并被引导到半导体晶片。 第二气体导入部具有设置在为第一气体导入部设置的导入管的任一侧的位置的两个喷淋喷嘴。 根据该真空处理装置，可以实现多个处理对象的高速处理。 此外，可以确保处理后的加工对象的面内均匀性。

公开(公告)号：US20110291726A1

公开(公告)日：2011-12-01

申请号：US13050652

申请日：2011-03-17

申请人： Woo-Seok KIM ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

发明人： Woo-Seok KIM ,  Do-Hyung Kim ,  Tae-Kwang Jang ,  Se-Hyung Jeon

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

摘要翻译： 一个占空比校正电路包括占空比转子电路，差分时钟发生器和电荷泵电路。 占空比电路响应于占空比控制信号校正输入时钟信号的占空比，并产生输出时钟信号。 差分时钟发生器基于输出时钟信号产生彼此相位差为180°的两个内部时钟信号。 电荷泵电路响应于内部时钟信号在差分模式下执行电荷泵操作以产生占空比控制信号。

公开(公告)号：US07920977B2

公开(公告)日：2011-04-05

申请号：US12043802

申请日：2008-03-06

申请人： Kyeong Dal Choi ,  Ji Kwang Lee ,  Seung Wook Lee ,  Chan Park ,  Woo Seok Kim

发明人： Kyeong Dal Choi ,  Ji Kwang Lee ,  Seung Wook Lee ,  Chan Park ,  Woo Seok Kim

IPC分类号： G01R19/00 ,  H01L39/24 ,  G01R27/00

CPC分类号： G01R15/202 ,  G01R19/0092

摘要： A noncontact method for measuring currents flowing through superconductive wires connected in parallel is provided. The method includes arranging hall sensors for measuring voltage levels based on magnetic fields generated around the superconductive wires, setting a matrix relation between the measured voltage values, values of currents flowing through the superconductive wires, and a variable matrix having variables defining relations between the voltage values and the current values, applying predetermined current levels to the superconductive wires a number of times and measuring voltage values through the hall sensors, substituting the predetermined current values and the measured voltage values into the matrix relation to calculate the variables of the variable matrix, and substituting the calculated variable matrix and unknown voltage values, measured by the hall sensors when unknown currents flow through the superconductive wires, into the matrix relation to calculate values of the unknown currents flowing through the superconductive wires.

摘要翻译： 提供了用于测量流过并联连接的超导线的电流的非接触方法。 该方法包括：布置霍尔传感器，用于基于在超导线周围产生的磁场测量电压电平，设定测得的电压值之间的矩阵关系，流过超导导线的电流值，以及具有变量的可变矩阵，该变量定义了电压 值和电流值，将预定电流电平施加到超导线数次，并通过霍尔传感器测量电压值，将预定电流值和测量电压值代入矩阵关系中，以计算可变矩阵的变量， 并且将未知电流通过超导线流过霍尔传感器测量的计算的可变矩阵和未知电压值代入矩阵关系，以计算流过超导线的未知电流的值。

公开(公告)号：US20110063128A1

公开(公告)日：2011-03-17

申请号：US12858691

申请日：2010-08-18

申请人： Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

发明人： Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

IPC分类号： H04J14/08

CPC分类号： H04J14/08 ,  H01L21/67069 ,  H01L21/67253

摘要： A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

摘要翻译： 室状态监视装置包括多个室，时分多路复用器，被配置为经由光纤探针从每个室接收光信号，以将每个光信号划分成具有预定持续时间的第一时隙，并将多路复用 用于产生OTDM信号的第一时隙;被配置为根据波长接收和分散OTDM信号以测量频谱信息的多输入光发射分光器;以及控制器，被配置为将分散的OTDM信号的频谱信息划分为第二时隙 以其间的预定时间间隔，根据室对第二时隙进行分类，以获得各个室的光信号的频谱信息，并且根据光信号的频谱信息来控制每个室中的端点检测 相应的房间。

公开(公告)号：US20080297210A1

公开(公告)日：2008-12-04

申请号：US11838952

申请日：2007-08-15

申请人： Woo-Seok Kim

发明人： Woo-Seok Kim

IPC分类号： H03B19/14

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00045 ,  H03K2005/00202 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/22

摘要： A clock multiplier includes a phase-frequency detector, a voltage-current converter, a duty ratio control circuit, a plurality of variable delay cells and an edge combiner. The phase-frequency detector generates control signals. The voltage-current converter converts the control signals to generate first and second current control voltages. The duty ratio control circuit modifies the duty ratio of an input clock signal based on the first and second current control voltages. Each of the variable delay cells generates a triangular wave voltage based on the modified input signal, generates a square wave voltage based on the triangular wave voltage to generate a delay signal. The edge combiner generates a plurality of multiplied clocks based on the delay signals from the variable delay cells.

摘要翻译： 时钟倍频器包括相位频率检测器，电压 - 电流转换器，占空比控制电路，多个可变延迟单元和边沿组合器。 相位检测器产生控制信号。 电压 - 电流转换器转换控制信号以产生第一和第二电流控制电压。 占空比控制电路基于第一和第二电流控制电压来修改输入时钟信号的占空比。 每个可变延迟单元基于修改的输入信号产生三角波电压，基于三角波电压产生方波电压以产生延迟信号。 边缘组合器基于来自可变延迟单元的延迟信号产生多个相乘的时钟。

公开(公告)号：US20080042698A1

公开(公告)日：2008-02-21

申请号：US11840515

申请日：2007-08-17

申请人： Woo-Seok Kim

发明人： Woo-Seok Kim

IPC分类号： H03K5/13 ,  H03B19/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/18

摘要： A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.

摘要翻译： 用于将输入时钟乘以N的时钟乘法器包括相位/频率检测器，时钟选择器和电压控制延迟线。 相位/频率检测器根据输入时钟与指示通过延迟输入时钟N次而产生的信号的计数信号之间的频率/相位差产生第一控制信号和第二控制信号。 时钟选择器根据输入时钟和计数信号选择输入时钟和反馈时钟之一。 电压控制延迟线根据基于第一控制信号和第二控制信号产生的控制电压来调整所选信号的延迟时间，并且基于调整后的信号输出反馈时钟。 当倍频比增加时，时钟倍频器不会累积输入时钟和输出时钟之间的频率/相位差。

公开(公告)号：US07227438B2

公开(公告)日：2007-06-05

申请号：US10905384

申请日：2004-12-30

申请人： Hee Suck Song ,  Woo Heng Heo ,  Jung Ho Park ,  Kyeong Dal Choi ,  Woo Seok Kim ,  Sung Hoon Kim

发明人： Hee Suck Song ,  Woo Heng Heo ,  Jung Ho Park ,  Kyeong Dal Choi ,  Woo Seok Kim ,  Sung Hoon Kim

IPC分类号： H01F6/00

CPC分类号： H01F36/00 ,  H01F6/06 ,  H01F2027/2838 ,  Y02E40/66 ,  Y10S336/01

摘要： The present invention discloses a superconducting wire transposition method and superconducting transformer whose winding is formed of superconducting wire to enable the formation of transpositions. The superconducting wire transposition method characterized of different winding start positions of at least two disks wound with a plurality of parallel superconductive wires, and usage of different superconducting wires for conductors to be connected between the disks, thereby forming transpositions outside of the disks. Preferably, part of the plurality of disks are rotatably assembled in pairs so as to form transpositions while maintaining a total number of windings equally. Therefore, according to the present invention, transpositions can be formed without bending or welding superconducting wires and thus, deteriorations in superconductivity can be prevented.

摘要翻译： 本发明公开了一种超导线转置法和超导变压器，其绕组由超导线形成以形成转置。 超导线转置方法的特征在于，用多个平行的超导线缠绕的至少两个盘的不同的绕组开始位置，以及用于连接在盘之间的导体的不同的超导线，从而在盘的外部形成转置。 优选地，多个盘的一部分成对地可旋转地组装，以便在保持总共数的绕组的同时形成转置。 因此，根据本发明，可以在不弯曲或焊接超导线的情况下形成转置，从而可以防止超导性的劣化。

公开(公告)号：US20060033591A1

公开(公告)日：2006-02-16

申请号：US11198691

申请日：2005-08-05

申请人： Woo-Seok Kim ,  Ju-Hyung Kim

发明人： Woo-Seok Kim ,  Ju-Hyung Kim

IPC分类号： H03L7/099

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/2472 ,  H03L1/022 ,  H03L7/099

摘要： A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.

摘要翻译： 压控振荡器包括偏置电路和延迟电路。 偏置电路可以产生具有基于输入电压信号的电压电平并且受偏置电路中产生的最大电流信号和最小电流信号的值约束的电平的偏置电压信号对。 延迟电路产生具有响应于偏置电压信号对而变化的频率的输出信号。 由于压控振荡器VCO的工作频率范围由偏置电路限制，所以VCO可以以减小的增益进行工作，并且可以将最大工作频率限制在预定的水平。 VCO还可以包括偏置电路中的PTAT电流发生器，其可以允许VCO基于温度补偿VCO输出频率的变化。

公开(公告)号：US08322019B2

公开(公告)日：2012-12-04

申请号：US12997652

申请日：2010-07-05

申请人： Kyeong Dal Choi ,  Ji Kwang Lee ,  Woo Seok Kim ,  Chan Park ,  Yung Il Kim

发明人： Kyeong Dal Choi ,  Ji Kwang Lee ,  Woo Seok Kim ,  Chan Park ,  Yung Il Kim

IPC分类号： H01B13/02 ,  H01B7/30 ,  H01B12/06 ,  H01B12/08

CPC分类号： H01B12/02 ,  H01B7/306 ,  Y02E40/641 ,  Y10T29/49014 ,  Y10T29/49194

摘要： Provided is a multiple transposition method for superconducting wire, by making each superconducting wire unit from second-generation superconducting wires that were firstly transposed and then transposing each superconducting wire unit in such a manner that the phase of each unit can be changed along the length, comprising preparing wires by making curves on superconducting wires in such a manner that the superconducting wires of a thin multiple layer grown epitaxially are slit in zigzags and then making the curves repeatedly and by machining the wires with a desired length; making first-transposed superconducting wire units by combining a plurality of the prepared wires such that curves of adjacent wires come in touch to each other and are superposed; preparing a superconducting wire unit bundle by arranging the first-transposed superconducting wires units and by locating a plurality of the first-transposed superconducting wire units in parallel along the length; and making a second transposition on the first-transposed superconducting wire units by rotating the plurality of superconducting wire units on the central axis of the superconducting wire unit bundle along the length to be twisted and combined with each other.

摘要翻译： 提供了一种用于超导线的多重转置方法，通过使来自第二代超导线的每个超导线单元首先被转置，然后以每个单元的相位沿着该长度改变的方式移位每个超导线单元， 包括通过在超导线上制作曲线来制备导线，使得外延生长的薄多层的超导线以锯齿形切割，然后反复制作曲线并通过机加工所需长度的线; 通过组合多个所制备的导线使相邻导线的曲线彼此接触并重叠而制造第一转置超导线单元; 通过布置第一转置超导线单元并通过沿着长度平行地定位多个第一转置的超导线单元来制备超导线单元束; 以及通过在所述超导线单元束的中心轴线上沿着要被扭曲并且彼此组合的长度旋转所述多个超导线单元，在所述第一转置的超导线单元上进行第二转置。