公开(公告)号：US10192881B2

公开(公告)日：2019-01-29

申请号：US14841328

申请日：2015-08-31

Applicant: Sang Wuk Park ,  Hyuk Kim ,  Kyoung Sub Shin ,  Gang Zhang

Inventor： Sang Wuk Park ,  Hyuk Kim ,  Kyoung Sub Shin ,  Gang Zhang

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region.

公开(公告)号：US09349747B2

公开(公告)日：2016-05-24

申请号：US14676843

申请日：2015-04-02

Applicant: Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

Inventor： Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form.

Abstract translation: 一种半导体器件包括具有在彼此垂直的第一和第二方向上延伸的上表面的基板，在第一方向上彼此间隔开的栅堆叠部分，栅堆叠部分包括在垂直方向上彼此间隔开的栅电极 并且具有在第二方向上延伸以具有锯齿形状的侧表面，通道区域穿过栅极堆叠部分并且设置成在第二方向上形成具有锯齿形状的列，至少两个沟道区域 在各栅极堆叠部分之间沿着第一方向线性排列的沟道区域和设置在彼此相邻并在第二方向上延伸以形成Z字形的栅叠层部分之间的源极区域。

公开(公告)号：US20110063128A1

公开(公告)日：2011-03-17

申请号：US12858691

申请日：2010-08-18

Applicant: Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

Inventor： Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

IPC: H04J14/08

CPC classification number: H04J14/08 ,  H01L21/67069 ,  H01L21/67253

Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract translation: 室状态监视装置包括多个室，时分多路复用器，被配置为经由光纤探针从每个室接收光信号，以将每个光信号划分成具有预定持续时间的第一时隙，并将多路复用 用于产生OTDM信号的第一时隙;被配置为根据波长接收和分散OTDM信号以测量频谱信息的多输入光发射分光器;以及控制器，被配置为将分散的OTDM信号的频谱信息划分为第二时隙 以其间的预定时间间隔，根据室对第二时隙进行分类，以获得各个室的光信号的频谱信息，并且根据光信号的频谱信息来控制每个室中的端点检测 相应的房间。

公开(公告)号：US20160233233A1

公开(公告)日：2016-08-11

申请号：US15134531

申请日：2016-04-21

Applicant: HYUK KIM ,  Sang Wuk Park ,  Kyoung Sub Shin

Inventor： HYUK KIM ,  Sang Wuk Park ,  Kyoung Sub Shin

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form.

公开(公告)号：US20160064407A1

公开(公告)日：2016-03-03

申请号：US14676843

申请日：2015-04-02

Applicant: Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

Inventor： Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

IPC: H01L27/115 ,  H01L29/78 ,  H01L27/02 ,  H01L29/792

CPC classification number: H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form.

Abstract translation: 一种半导体器件包括具有在彼此垂直的第一和第二方向上延伸的上表面的基板，在第一方向上彼此间隔开的栅堆叠部分，栅堆叠部分包括在垂直方向上彼此间隔开的栅电极 并且具有在第二方向上延伸以具有锯齿形状的侧表面，通道区域穿过栅极堆叠部分并且设置成在第二方向上形成具有锯齿形状的列，至少两个沟道区域 在各栅极堆叠部分之间沿着第一方向线性排列的沟道区域和设置在彼此相邻并在第二方向上延伸以形成Z字形的栅叠层部分之间的源极区域。

公开(公告)号：US08872059B2

公开(公告)日：2014-10-28

申请号：US13220084

申请日：2011-08-29

Applicant: Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

Inventor： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

IPC: B23K26/03 ,  B23K26/04 ,  H01L21/00 ,  B23K26/06 ,  H01L21/66 ,  H01J37/32 ,  B23K26/36

CPC classification number: B23K26/0661 ,  B23K26/032 ,  B23K26/361 ,  H01J37/32972 ,  H01L22/12 ,  H01L22/26

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract translation: 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。

公开(公告)号：US08304264B2

公开(公告)日：2012-11-06

申请号：US12858691

申请日：2010-08-18

Applicant: Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

Inventor： Sang-Wuk Park ,  Woo-Seok Kim ,  Yong-Jin Kim

IPC: G01R31/26

CPC classification number: H04J14/08 ,  H01L21/67069 ,  H01L21/67253

Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract translation: 室状态监视装置包括多个室，时分多路复用器，被配置为经由光纤探针从每个室接收光信号，以将每个光信号划分成具有预定持续时间的第一时隙，并将多路复用 用于产生OTDM信号的第一时隙;被配置为根据波长接收和分散OTDM信号以测量频谱信息的多输入光发射分光器;以及控制器，被配置为将分散的OTDM信号的频谱信息划分为第二时隙 以其间的预定时间间隔，根据室对第二时隙进行分类，以获得各个室的光信号的频谱信息，并且根据光信号的频谱信息来控制每个室中的端点检测 相应的房间。

公开(公告)号：US20160071855A1

公开(公告)日：2016-03-10

申请号：US14841328

申请日：2015-08-31

Applicant: Sang Wuk Park ,  Hyuk Kim ,  Kyoung Sub Shin ,  Gang Zhang

Inventor： Sang Wuk Park ,  Hyuk Kim ,  Kyoung Sub Shin ,  Gang Zhang

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region.

Abstract translation: 半导体器件包括设置在衬底上并且在第一方向上彼此间隔开的栅极叠层，隔离区域插入在栅极堆叠之间; 沟道区域穿过栅极堆叠并设置在每个栅极堆叠内; 以及与所述分离区域相邻的引导区域，穿过所述栅极堆叠的至少一部分，并且具有朝向所述分离区域弯曲的弯曲部分。

公开(公告)号：US20120055908A1

公开(公告)日：2012-03-08

申请号：US13220084

申请日：2011-08-29

Applicant: Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

Inventor： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

IPC: B23K26/36 ,  B23K26/04

CPC classification number: B23K26/0661 ,  B23K26/032 ,  B23K26/361 ,  H01J37/32972 ,  H01L22/12 ,  H01L22/26

Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

Abstract translation: 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。