公开(公告)号：US07447058B2

公开(公告)日：2008-11-04

申请号：US11341429

申请日：2006-01-30

申请人： Yasuhiko Maki ,  Koji Shimosako

发明人： Yasuhiko Maki ,  Koji Shimosako

IPC分类号： G11C11/00

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.

摘要翻译： 每个存储单元具有一对反相器，其输入和输出彼此连接并分别保存在作为反相器的输出的存储节点中的互补数据。 在将补充数据分别写入存储节点的写入操作中，功率控制电路设置具有写入低电平的存储节点的逆变器的电源电压低于具有该等级的逆变器的电源电压 写入高级别的存储节点。 由于具有写入低电平的存储节点的逆变器的电力供应能力降低，所以存储节点的电压容易变为低电平。 也就是说，可以提高存储单元的写入裕度。

公开(公告)号：US06239647B1

公开(公告)日：2001-05-29

申请号：US09440666

申请日：1999-11-16

申请人： Takako Kagiwata ,  Toshiyuki Uetake ,  Yasuhiko Maki

发明人： Takako Kagiwata ,  Toshiyuki Uetake ,  Yasuhiko Maki

IPC分类号： H03K1772

CPC分类号： G11C8/10

摘要： A decoder circuit includes a detecting device which detects a selecting signal for selecting the decoder circuit, a clock-signal supplying device which supplies a clock signal, and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when the detecting device detects the selecting signal.

摘要翻译： 解码器电路包括：检测用于选择解码器电路的选择信号的检测装置;提供时钟信号的时钟信号提供装置;以及解码信号输出装置，其根据时钟信号的定时输出解码信号 检测装置检测选择信号。

公开(公告)号：US4906868A

公开(公告)日：1990-03-06

申请号：US269413

申请日：1988-11-10

申请人： Yasuhiko Maki ,  Osamu Nomura

发明人： Yasuhiko Maki ,  Osamu Nomura

IPC分类号： G11C11/417 ,  G05F3/22 ,  G11C7/06 ,  G11C8/08 ,  G11C11/407 ,  H03K19/00 ,  H03K19/0944

CPC分类号： G05F3/22 ,  G11C7/062 ,  G11C8/08 ,  H03K19/0027 ,  H03K19/09448

摘要： A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result, the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.

公开(公告)号：US07421364B2

公开(公告)日：2008-09-02

申请号：US11335697

申请日：2006-01-20

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G01R31/00 ,  G01R31/14

CPC分类号： G11C29/50012 ,  G11C11/41 ,  G11C29/16 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated circuit device of the invention, has a memory macro which during normal operation latches an input address in response to a control pulse and generates data output corresponding to the input address, and a test control circuit 22 which during testing performs memory macro characteristic tests. A ring oscillator is configured by connecting a prescribed number of stages including one or more memory macro units, having a memory macro and a pulse generation circuit which during testing generates a control pulse for tests in response to an input pulse, and the test control circuit measures the oscillation frequency or period of the ring oscillator.

摘要翻译： 本发明的集成电路装置具有存储器宏，其在正常操作期间响应于控制脉冲锁存输入地址并产生对应于输入地址的数据输出;以及测试控制电路22，其在测试期间执行存储器宏特性测试 。 环形振荡器通过连接包括具有存储器宏的一个或多个存储器宏单元的规定数量级和在测试期间产生用于响应于输入脉冲进行测试的控制脉冲的脉冲生成电路而配置的测试控制电路 测量环形振荡器的振荡频率或周期。

公开(公告)号：US07327599B2

公开(公告)日：2008-02-05

申请号：US11494746

申请日：2006-07-28

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： Included are first and second inverters 1L, 1R, a first selection transistor N1 controlling a connection of an output terminal of the first inverter 1L to a bit line 11, and a second selection transistor N2 controlling a connection of an output terminal of the second inverter 1R to a bit line 12, wherein the first inverter 1L having a first load transistor P1 and a first drive transistor N3 and the second inverter 1R having a second load transistor P2 and a second drive transistor N4, function as a memory cell 1, and a ratio of a driving current quantity that can be outputted in an ON-state of the first drive transistor N3 to a driving current quantity that can be outputted in an ON-state of the first selection transistor N1, is larger than a first predetermined value.

摘要翻译： 包括第一和第二反相器1L，R1，控制第一反相器11L的输出端与位线11的连接的第一选择晶体管N 1和控制输出的连接的第二选择晶体管N 2 第二反相器1R的端子到位线12，其中第一反相器L1具有第一负载晶体管P 1和第一驱动晶体管N 3，第二反相器1R具有第二负载晶体管P 2和第二驱动 用作存储单元1的晶体管N 4，以及可以在第一驱动晶体管N 3的导通状态下输出的驱动电流量与可以在导通状态的导通状态下输出的驱动电流量的比率 第一选择晶体管N 1大于第一预定值。

公开(公告)号：US06809404B2

公开(公告)日：2004-10-26

申请号：US10393917

申请日：2003-03-24

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： H01L2358

CPC分类号： G11C29/812 ,  G11C17/14 ,  G11C17/143 ,  G11C29/848

摘要： A semiconductor device with laser-programmable fuses for repairing a memory defect found after production, in which guard rings and fuse patterns are designed to take up less chip space. The semiconductor device has a fuse pattern running parallel to the longitudinal axis of a rectangular guard ring, and patterns branching from the fuse pattern and drawn out of the guard ring in the direction perpendicular to that axis. The semiconductor device also has a plurality of memory cell arrays, each coupled to an I/O port for receiving and sending memory signals. One of those arrays is reserved as a redundant memory cell array for repair purposes. The device further has switch circuits for switching the connection between the I/O ports and memory cell arrays, selecting either default memory cell arrays of the I/O ports or their adjacent memory cell arrays, including the redundant memory cell array.

摘要翻译： 具有激光可编程保险丝的半导体器件用于修复生产后发现的存储器缺陷，其中保护环和保险丝图案被设计成占用较少的芯片空间。 半导体器件具有平行于矩形保护环的纵向轴线延伸的熔丝图案，以及从熔丝图案分支并沿垂直于该轴线的方向从保护环拉出的图案。 半导体器件还具有多个存储单元阵列，每个存储单元阵列耦合到I / O端口，用于接收和发送存储器信号。 其中一个数组被保留作为用于修复目的的冗余存储单元阵列。 该装置还具有用于切换I / O端口和存储单元阵列之间的连接的开关电路，选择I / O端口的默认存储单元阵列或其相邻的存储单元阵列，包括冗余存储单元阵列。

公开(公告)号：US4757474A

公开(公告)日：1988-07-12

申请号：US11268

申请日：1987-01-21

申请人： Isao Fukushi ,  Yasuhiko Maki

发明人： Isao Fukushi ,  Yasuhiko Maki

IPC分类号： G11C29/00 ,  G11C11/40

CPC分类号： G11C29/806

摘要： A semiconductor memory device includes a redundancy circuit having upper address bit input terminals receiving upper address bit, lower address bit input terminals receiving lower address bits, a regular memory cell array having a plurality of word lines and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. A redundancy memory cell array is provided having a plurality of word and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. The capacity of the redundancy memory cell array being smaller than the regular memory cell array. A first selection circuit selects a word or bit line in the regular memory cell array in accordance with the upper and lower address bits. A second selection circuit select a word or bit line in the redundancy memory cell array in accordance with the lower address bits. A redundancy address programming circuit programs the upper address bits corresponding to defective memory cells in the regular memory cell array. A control circuit compares the input upper address bits with the programmed upper address bits and controls the first and second selection circuits to inhibit the selection of the word or bit lines in the regular memory cell array. A predetermined word or bit line in the redundancy memory cell array is selected therefor when each of the input upper address bits coincides with each of the programmed upper address bits.

公开(公告)号：US07995407B2

公开(公告)日：2011-08-09

申请号：US12177650

申请日：2008-07-22

申请人： Yasuhiko Maki

发明人： Yasuhiko Maki

IPC分类号： G11C29/00

CPC分类号： G11C5/14 ,  G11C29/83

摘要： A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and to which a third power supply voltage is supplied, a redundant cell array that includes a redundant memory cell to which one of the first power supply voltage and the second power supply voltage is supplied and to which the third power supply voltage is supplied, and a power supply control circuit that controls supply of the first power supply voltage and the second power supply voltage to the regular cell array and the redundant cell array, wherein a difference between the second power supply voltage and the third power supply voltage is smaller than a difference between the first power supply voltage and the third power supply voltage.

摘要翻译： 一种半导体存储器件，包括常规单元阵列，其包括提供第一电源电压和第二电源电压中的一个并且被提供第三电源电压的常规存储单元，冗余单元阵列包括： 提供第一电源电压和第二电源电压之一并且提供第三电源电压的冗余存储单元，以及控制第一电源电压和第二电力供应的电源控制电路 向正常单元阵列和冗余单元阵列提供电压，其中第二电源电压和第三电源电压之间的差小于第一电源电压和第三电源电压之间的差。

公开(公告)号：US20090046523A1

公开(公告)日：2009-02-19

申请号：US12177650

申请日：2008-07-22

申请人： Yasuhiko MAKI

发明人： Yasuhiko MAKI

IPC分类号： G11C29/04 ,  G11C5/14

CPC分类号： G11C5/14 ,  G11C29/83

摘要： A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and to which a third power supply voltage is supplied, a redundant cell array that includes a redundant memory cell to which one of the first power supply voltage and the second power supply voltage is supplied and to which the third power supply voltage is supplied, and a power supply control circuit that controls supply of the first power supply voltage and the second power supply voltage to the regular cell array and the redundant cell array, wherein a difference between the second power supply voltage and the third power supply voltage is smaller than a difference between the first power supply voltage and the third power supply voltage.

摘要翻译： 一种半导体存储器件，包括常规单元阵列，其包括提供第一电源电压和第二电源电压中的一个并且被提供第三电源电压的常规存储单元，冗余单元阵列包括： 提供第一电源电压和第二电源电压之一并且提供第三电源电压的冗余存储单元，以及控制第一电源电压和第二电力供应的电源控制电路 向正常单元阵列和冗余单元阵列提供电压，其中第二电源电压和第三电源电压之间的差小于第一电源电压和第三电源电压之间的差。

公开(公告)号：US07457182B2

公开(公告)日：2008-11-25

申请号：US11438447

申请日：2006-05-23

申请人： Yasuhiko Maki ,  Toshiyuki Uetake

发明人： Yasuhiko Maki ,  Toshiyuki Uetake

IPC分类号： G11C7/02

CPC分类号： H01L27/1104 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory including a sense amplifier circuit for reading the data stored in memory cells and particularly to a semiconductor memory including a self-timing circuit for improving margin for reading data by controlling activation timing of the sense amplifier drive signal in accordance with characteristics of internal memory cells.

摘要翻译： 一种半导体存储器，包括用于读取存储在存储单元中的数据的读出放大器电路，特别是涉及包括用于通过根据内部特性控制读出放大器驱动信号的激活定时来提高读取数据的余量的半自动计时电路的半导体存储器 记忆细胞