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1.发明授权公开(公告)号：US07376773B2
公开(公告)日：2008-05-20
申请号：US10884145
申请日：2004-07-02
Applicant: Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
Inventor： Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
IPC: G06F13/12
CPC classification number: G06K19/07 , G06K7/10297 , G06K19/077 , G06K19/07732 , G06K19/07733
Abstract: A multi-standard protocol storage device can include a non-volatile memory, a first interface controller, a second interface controller, and at least one pin. The non-volatile memory can be accessed according to a non-volatile memory protocol. The first interface controller can be configured to convert first commands in a first standardized protocol to the non-volatile memory protocol and the second interface controller can be configured to convert second commands in a second standardized protocol to the non-volatile memory protocol. The at least one pin of the device is configured to conduct a recognition signal thereon indicating whether the first or second standardized protocol is used by a host coupled thereto and that conducts data signals according to the first and second standardized protocols.
Abstract translation: 多标准协议存储设备可以包括非易失性存储器，第一接口控制器，第二接口控制器和至少一个引脚。 可以根据非易失性存储器协议访问非易失性存储器。 可以将第一接口控制器配置为将第一标准化协议中的第一命令转换为非易失性存储器协议，并且第二接口控制器可被配置为将第二标准化协议中的第二命令转换为非易失性存储器协议。 设备的至少一个引脚被配置为在其上进行识别信号，指示第一或第二标准化协议是否被耦合到其的主机使用，并且根据第一和第二标准化协议进行数据信号。
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2.发明授权Non-volatile semiconductor memory device for connecting to serial advanced technology attachment cable 有权用于连接串行高级技术附件电缆的非易失性半导体存储器件公开(公告)号：US06853573B2
公开(公告)日：2005-02-08
申请号：US10453989
申请日：2003-06-04
Applicant: Seong-hyun Kim , Sam-yong Bahng , Yong-hyeon Kim , Tae-Keun Jeon
Inventor： Seong-hyun Kim , Sam-yong Bahng , Yong-hyeon Kim , Tae-Keun Jeon
CPC classification number: G06F3/0661 , G06F3/0613 , G06F3/0679
Abstract: A serial advanced technology attachment (SATA) storage device supports an SATA protocol that provides for high data transfer speed. The storage device is for connecting to an SATA cable, and includes at least one non-volatile semiconductor memory device for storing data therein; an SATA adapter, connected to the SATA cable, for transferring/receiving data signals to/from the SATA cable; a memory controller for controlling the non-volatile semiconductor memory device in response to data signals transferred from the SATA adapter; and an SATA device controller, connected between the SATA adapter and the memory controller, for interfacing transmitted/received data signals between the SATA adapter and the memory controller.
Abstract translation: 串行高级技术附件（SATA）存储设备支持SATA协议，提供高数据传输速度。 存储设备用于连接到SATA电缆，并且包括用于在其中存储数据的至少一个非易失性半导体存储器件; 连接到SATA电缆的SATA适配器，用于向/从SATA电缆传输/接收数据信号; 存储器控制器，用于响应于从SATA适配器传送的数据信号来控制非易失性半导体存储器件; 以及连接在SATA适配器和存储器控制器之间的SATA设备控制器，用于在SATA适配器和存储器控制器之间连接发送/接收的数据信号。
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3.发明申请公开(公告)号：US20050005045A1
公开(公告)日：2005-01-06
申请号：US10884145
申请日：2004-07-02
Applicant: Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
Inventor： Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
IPC: G06F13/00 , G06K19/07 , G06K19/077 , G06F13/14
CPC classification number: G06K19/07 , G06K7/10297 , G06K19/077 , G06K19/07732 , G06K19/07733
Abstract: A multi-standard protocol storage device can include a non-volatile memory, a first interface controller, a second interface controller, and at least one pin. The non-volatile memory can be accessed according to a non-volatile memory protocol. The first interface controller can be configured to convert first commands in a first standardized protocol to the non-volatile memory protocol and the second interface controller can be configured to convert second commands in a second standardized protocol to the non-volatile memory protocol. The at least one pin of the device is configured to conduct a recognition signal thereon indicating whether the first or second standardized protocol is used by a host coupled thereto and that conducts data signals according to the first and second standardized protocols.
Abstract translation: 多标准协议存储设备可以包括非易失性存储器，第一接口控制器，第二接口控制器和至少一个引脚。 可以根据非易失性存储器协议访问非易失性存储器。 可以将第一接口控制器配置为将第一标准化协议中的第一命令转换为非易失性存储器协议，并且第二接口控制器可被配置为将第二标准化协议中的第二命令转换为非易失性存储器协议。 设备的至少一个引脚被配置为在其上进行识别信号，指示第一或第二标准化协议是否被耦合到其的主机使用，并且根据第一和第二标准化协议进行数据信号。
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4.发明授权公开(公告)号：US08370611B2
公开(公告)日：2013-02-05
申请号：US12046888
申请日：2008-03-12
Applicant: Sung-Up Choi , Se-Jin Ahn , Yong-Hyeon Kim
Inventor： Sung-Up Choi , Se-Jin Ahn , Yong-Hyeon Kim
IPC: G06F15/177 , G06F12/00 , G06F9/00 , G06F12/02
CPC classification number: G11C7/1045 , G06F9/4401 , G06F12/06 , G06F2212/2022
Abstract: Provided is a memory card device. The memory card device includes a flash memory and a controller. The flash memory includes a boot area storing boot data, and a user area storing user data. The controller accesses the boot area or the user area according to an external command. Boot data can be stored in a memory card integrated in an electronic device. Also, when a host requests an access to boot data/user data stored in the memory card, the boot data/user data can be accessed under control of the controller.
Abstract translation: 提供了一种存储卡装置。 存储卡装置包括闪存和控制器。 闪速存储器包括存储引导数据的引导区域和存储用户数据的用户区域。 控制器根据外部命令访问引导区域或用户区域。 引导数据可以存储在集成在电子设备中的存储卡中。 此外，当主机请求访问存储在存储卡中的引导数据/用户数据时，可以在控制器的控制下访问引导数据/用户数据。
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5.发明授权Memory system that detects bit errors due to read disturbance and methods thereof 有权用于检测由读取干扰引起的位错误的存储器系统及其方法公开(公告)号：US08316278B2
公开(公告)日：2012-11-20
申请号：US12141611
申请日：2008-06-18
Applicant: Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
Inventor： Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
IPC: G11C21/00
CPC classification number: G11C16/26 , G06F11/1068 , G11C16/0483 , G11C29/76
Abstract: Methods and memory systems are provided that detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
Abstract translation: 提供了检测由读取干扰引起的位错误的方法和存储器系统。 读取存储器系统中闪存的主页面。 检测并纠正从主页读取的数据中的位错误。 在读取主页的同时，在从闪存的虚拟页读取的数据中检测到位错误。
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Patent Agency Ranking
公开(公告)号：US07711865B2
公开(公告)日：2010-05-04
申请号：US12107630
申请日：2008-04-22
Applicant: Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
Inventor： Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
CPC classification number: G06K19/07 , G06K7/10297 , G06K19/077 , G06K19/07732 , G06K19/07733
Abstract: A movable storage device combined with a smart card can include a plurality of signal pins that are connected to at least one of a plurality of memory card hosts that use different communications protocols from each other or a smart card host, and at least one signal pin that is used as a mode distinguishing pin. A mode deciding unit can decide on an operation mode, which can be a smart card mode and/or a memory card mode based on a level of a first initial input signal received from the mode distinguishing pin. A smart card module can communicate with a smart card host in a smart card mode and a memory card module can be interfaced with memory card hosts, and communicates with a memory card host connected in a memory card mode and stores data.
Abstract translation: 与智能卡组合的可移动存储设备可以包括多个信号引脚，其连接到使用彼此不同的通信协议或智能卡主机的多个存储卡主机中的至少一个，以及至少一个信号引脚 用作模式识别引脚。 模式判定单元可以基于从模式识别引脚接收的第一初始输入信号的电平来决定可以是智能卡模式和/或存储卡模式的操作模式。 智能卡模块可以以智能卡模式与智能卡主机进行通信，并且存储卡模块可以与存储卡主机连接，并且与以存储卡模式连接的存储卡主机通信并存储数据。
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7.发明申请MEMORY SYSTEM THAT DETECTS BIT ERRORS DUE TO READ DISTURBANCE AND METHODS THEREOF 审中-公开检测到读取干扰的位错误的存储器系统及其方法公开(公告)号：US20140115419A1
公开(公告)日：2014-04-24
申请号：US13658301
申请日：2012-10-23
Applicant: Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
Inventor： Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
CPC classification number: G11C7/14 , G06F11/1048 , H03M13/09 , H03M13/13
Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
Abstract translation: 提供了可以检测由于读取干扰引起的位错误的方法和存储器系统。 读取存储器系统中闪存的主页面。 检测并纠正从主页读取的数据中的位错误。 在读取主页的同时，在从闪存的虚拟页读取的数据中检测到位错误。
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8.发明申请WRITE AND MERGE METHODS IN MEMORY CARD SYSTEMS FOR REDUCING THE NUMBER OF PAGE COPIES 有权用于减少页数的存储卡系统中的写和合并方法公开(公告)号：US20090193191A1
公开(公告)日：2009-07-30
申请号：US12358374
申请日：2009-01-23
Applicant: Kyoung-Ryun BAE , Hee-Tak SHIN , Jung-Hoon KIM , Jong-hwan LEE , Yong-Hyeon KIM , Chang-Eun CHOI
Inventor： Kyoung-Ryun BAE , Hee-Tak SHIN , Jung-Hoon KIM , Jong-hwan LEE , Yong-Hyeon KIM , Chang-Eun CHOI
CPC classification number: G06F12/0246
Abstract: A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that corresponds to a first data block including the page; receiving an update request for the page; and performing a write operation on a second log block that corresponds to the first data block. The memory card system includes: at least one non-volatile memory including a data block and a log block for updating the data block; and a memory controller controlling an operation of the non-volatile memory. During a write operation for a predetermined page, the controller controls writing of a first log block corresponding to a first data block including the predetermined page, and controls writing of a second log block during an update operation of the predetermined page.
Abstract translation: 公开了一种存储卡系统和相关的写入方法。 该方法包括接收对预定页面的写入请求; 对与包括所述页面的第一数据块相对应的第一日志块执行写入操作; 接收页面的更新请求; 以及对与所述第一数据块相对应的第二日志块执行写入操作。 存储卡系统包括：至少一个包括用于更新数据块的数据块和日志块的非易失性存储器; 以及控制非易失性存储器的操作的存储器控制器。 在预定页面的写入操作期间，控制器控制对应于包括预定页面的第一数据块的第一日志块的写入，并且在预定页面的更新操作期间控制第二日志块的写入。
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9.发明申请MEMORY SYSTEM THAT DETECTS BIT ERRORS DUE TO READ DISTURBANCE AND METHODS THEREOF 有权检测到读取干扰的位错误的存储器系统及其方法公开(公告)号：US20080316822A1
公开(公告)日：2008-12-25
申请号：US12141611
申请日：2008-06-18
Applicant: Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
Inventor： Se-Jin Ahn , Yong-Hyeon Kim , Sung-Up Choi , Yong-Kyeong Kim
IPC: G11C16/06
CPC classification number: G11C16/26 , G06F11/1068 , G11C16/0483 , G11C29/76
Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
Abstract translation: 提供了可以检测由于读取干扰引起的位错误的方法和存储器系统。 读取存储器系统中闪存的主页面。 检测并纠正从主页读取的数据中的位错误。 在读取主页的同时，在从闪存的虚拟页读取的数据中检测到位错误。
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公开(公告)号：US20080191034A1
公开(公告)日：2008-08-14
申请号：US12107630
申请日：2008-04-22
Applicant: Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
Inventor： Yong-hyeon Kim , Tae-keun Jeon , Seong-hyun Kim
IPC: G06K19/067
CPC classification number: G06K19/07 , G06K7/10297 , G06K19/077 , G06K19/07732 , G06K19/07733
Abstract: A movable storage device combined with a smart card can include a plurality of signal pins that are connected to at least one of a plurality of memory card hosts that use different communications protocols from each other or a smart card host, and at least one signal pin that is used as a mode distinguishing pin. A mode deciding unit can decide on an operation mode, which can be a smart card mode and/or a memory card mode based on a level of a first initial input signal received from the mode distinguishing pin. A smart card module can communicate with a smart card host in a smart card mode and a memory card module can be interfaced with memory card hosts, and communicates with a memory card host connected in a memory card mode and stores data.
Abstract translation: 与智能卡组合的可移动存储设备可以包括多个信号引脚，其连接到使用彼此不同的通信协议或智能卡主机的多个存储卡主机中的至少一个，以及至少一个信号引脚 用作模式识别引脚。 模式判定单元可以基于从模式识别引脚接收的第一初始输入信号的电平来决定可以是智能卡模式和/或存储卡模式的操作模式。 智能卡模块可以以智能卡模式与智能卡主机进行通信，并且存储卡模块可以与存储卡主机连接，并且与以存储卡模式连接的存储卡主机通信并存储数据。
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