公开(公告)号：US07698586B2

公开(公告)日：2010-04-13

申请号：US11335619

申请日：2006-01-20

Applicant: Won-Tae Kim ,  Sam-Yong Bahng ,  Tae-Jin Yoo ,  Jong-Keun Ahn ,  Yong-Ji Kim ,  Sang-Hee Lee ,  Min-Soo Kang

Inventor： Won-Tae Kim ,  Sam-Yong Bahng ,  Tae-Jin Yoo ,  Jong-Keun Ahn ,  Yong-Ji Kim ,  Sang-Hee Lee ,  Min-Soo Kang

IPC: G06F1/00

CPC classification number: G06F1/3228 ,  G06F1/3268 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D50/20

Abstract: A portable system, method thereof, and a power consumption controller for controlling power consumption in a portable system are described. The portable system may include a storage unit, a module processing data, and a controller regulating power supplied to the module. The controller may regulate the module to perform a backup operation when a power saving mode begins and to interrupt the power after the backup operation is completed.

Abstract translation: 描述了便携式系统及其方法，以及用于控制便携式系统中的功耗的功耗控制器。 便携式系统可以包括存储单元，模块处理数据和调节供应给模块的功率的控制器。 当省电模式开始时，控制器可以调节模块执行备份操作，并在备份操作完成后中断电源。

公开(公告)号：US20080183966A1

公开(公告)日：2008-07-31

申请号：US11954769

申请日：2007-12-12

Applicant: Kyu Hyun SHIM ,  Nam Phil JO ,  Sam-Yong BAHNG

Inventor： Kyu Hyun SHIM ,  Nam Phil JO ,  Sam-Yong BAHNG

IPC: G06F12/00

CPC classification number: G11C16/349 ,  G11C16/3495

Abstract: An electronic system for informing the term of validity and endurance includes a host and a semiconductor memory card. The semiconductor memory card informs a user of the term of validity and/or the endurance thereof, so that the user can move data stored in the semiconductor memory card to another memory device before the life span of the semiconductor memory card expires based on data about the term of validity and/or the endurance, thereby safely preserving the data.

Abstract translation: 用于通知有效期和耐久性的电子系统包括主机和半导体存储卡。 半导体存储卡向用户通知有效期限和/或其耐久性，使得用户可以在半导体存储卡的寿命期限之前将存储在半导体存储卡中的数据移动到另一个存储器件，基于关于 有效期和/或耐久性，从而安全地保存数据。

公开(公告)号：US20070274137A1

公开(公告)日：2007-11-29

申请号：US11670285

申请日：2007-02-01

Applicant: Sung-Ho Park ,  Sam-Yong Bahng ,  Seok-Won Heo

Inventor： Sung-Ho Park ,  Sam-Yong Bahng ,  Seok-Won Heo

IPC: G11C7/06

CPC classification number: G11C7/1051 ,  G11C7/1069

Abstract: A memory card including a pad, a drive circuit activating the pad in accordance With an input signal, and a controller regulating a drive voltage level and a drive point of an output signal generated from the drive circuit in accordance with a voltage level of the output signal of the drive circuit. The controller may include a delay circuit, generating a second clock signal by delaying a first clock signal provided from an external source and generating a second clock signal from the first clock signal. The controller may further include a detection circuit capturing the voltage level of the output signal of the drive circuit as a first detection voltage in sync with the first clock signal and capturing the voltage level of the output signal of the drive circuit as a second detection voltage in sync with the second dock signal. The controller may additionally include a drive control circuit regulating the drive voltage level and the drive point of the output signal of the drive circuit in response to the first and second detection voltages.

Abstract translation: 一种存储卡，包括：焊盘，根据输入信号激活焊盘的驱动电路;以及控制器，其根据输出的电压电平来调节驱动电压电平和从驱动电路产生的输出信号的驱动点 驱动电路的信号。 控制器可以包括延迟电路，通过延迟从外部源提供的第一时钟信号并从第一时钟信号产生第二时钟信号来产生第二时钟信号。 控制器还可以包括检测电路，其将驱动电路的输出信号的电压电平与第一时钟信号同步地作为第一检测电压，并将驱动电路的输出信号的电压电平作为第二检测电压 与第二停靠信号同步。 控制器还可以包括响应于第一和第二检测电压来调节驱动电压电平和驱动电路的输出信号的驱动点的驱动控制电路。

公开(公告)号：US20060231835A1

公开(公告)日：2006-10-19

申请号：US11398313

申请日：2006-04-05

Applicant: Jin-Hyeok Choi ,  Sam-Yong Bahng

Inventor： Jin-Hyeok Choi ,  Sam-Yong Bahng

IPC: H01L23/58

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality of via contacts formed in the inter-metal insulating layer, and a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.

Abstract translation: 半导体器件包括形成在半导体衬底上的多层，多层包括第一电路图案，用于测试半导体器件的第二电路图案，形成在多层的预定区域上的第二电路，形成在多层的预定区域上的金属间绝缘层 所述第二电路图案，形成在所述金属间绝缘层中的多个通孔接头以及设置在所述金属间绝缘层上的多个ROM接口焊盘，其中所述多个ROM接口焊盘与所述第二电路图形电连接 通过多个通孔触点，并且彼此分离。

公开(公告)号：US20050202855A1

公开(公告)日：2005-09-15

申请号：US11061903

申请日：2005-02-18

Applicant: Jin-Hyeok Choi ,  Sam-Yong Bahng

Inventor： Jin-Hyeok Choi ,  Sam-Yong Bahng

IPC: G11C11/40 ,  H04B1/06 ,  H04B1/16 ,  H04B7/00

CPC classification number: G11C29/32

Abstract: A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semiconductor device, and reduce power consumption in a standby state.

Abstract translation: 数据存储电路和数据保存方法，用于在半导体器件使用测试扫描链处于睡眠模式时保存数据，其中数据存储电路包括睡眠模式控制单元和扫描链单元，睡眠模式控制 响应于从外部接收的测试控制信号和睡眠模式控制信号中的一个输出扫描控制信号和扫描时钟信号，当接收到输出数据信号时，将输出数据信号存储在存储器中，并输出 测试图形数据信号作为扫描数据信号，当接收到测试图形数据信号时，扫描链单元将存储在扫描链单元内的正常数据信号作为输出数据信号输出到睡眠模式控制单元，或者接收并输出 根据扫描控制信号和扫描时钟信号将数据信号扫描到组合电路单元，数据存储电路和数据保存方法防止数据丢失为 半通道模式，并且在待机状态下降低功耗。

公开(公告)号：US06285717B1

公开(公告)日：2001-09-04

申请号：US08864565

申请日：1997-05-29

Applicant: Sam-yong Bahng ,  Jung-chul Kim

Inventor： Sam-yong Bahng ,  Jung-chul Kim

IPC: H04N712

CPC classification number: H04N21/4305 ,  H04N5/4401 ,  H04N5/46 ,  H04N9/64 ,  H04N9/68 ,  H04N11/143 ,  H04N11/162 ,  H04N11/20 ,  H04N19/61

Abstract: A digital video encoder for a digital video system wherein digital video data output from an MPEG decoder is input and an analogue composite video baseband signal (CVBS) is output comprises first selection means for selectively outputting first and second clocks in response to a first selection signal, signal dividing means for dividing the input digital video data into a luminance signal and a chrominance signal in response to the output of the first selection means, luminance signal processing means for regulating the gain and offset of the luminance signal, adding a synchronizing signal to the regulated luminance signal, and filtering a low band component of the luminance signal to output the filtered signal as a digital luminance signal, chrominance signal processing means for regulating the gain of the chrominance signal, interpolating the gain-regulated chrominance signal, producing color difference signals, interpolating the produced color difference signals, filtering a low band component of the interpolated color difference signals, and modulating the filtered color difference signals, to thereby output the modulated signal as a digital chrominance signal, signal synthesizing means for synthesizing the digital luminance and chrominance signals and outputting the synthesized signal, first digital-to-analogue converting means for converting the synthesized signal to an analogue signal and outputting the converted signal as the analogue composite video baseband signal, and controlling means for outputting the first selection signal corresponding to the size and input speed of the input digital video signal. Therefore, synchronization is easy, costs are reduced, various OSD functions are provided, a high-quality image is provided, and the displayed image is undistorted.

Abstract translation: 一种用于数字视频系统的数字视频编码器，其中输入从MPEG解码器输出的数字视频数据并输出模拟复合视频基带信号（CVBS），包括用于响应于第一选择信号选择性地输出第一和第二时钟的第一选择装置 信号分割装置，用于响应于第一选择装置的输出将输入的数字视频数据分成亮度信号和色度信号;亮度信号处理装置，用于调节亮度信号的增益和偏移，将同步信号加到 调节亮度信号，并对亮度信号的低频带分量进行滤波，以输出滤波后的信号作为数字亮度信号;色度信号处理装置，用于调节色度信号的增益，内插增益调节色度信号，产生色差 信号，内插产生的色差信号，过滤低禁令 d分量，并且调制滤波后的色差信号，从而输出调制信号作为数字色度信号;信号合成装置，用于合成数字亮度和色度信号，并输出合成信号，首先数字转换为 - 用于将合成信号转换为模拟信号并输出​​转换的信号作为模拟复合视频基带信号的分析转换装置，以及用于输出与输入数字视频信号的大小和输入速度对应的第一选择信号的控制装置。 因此，同步容易，成本降低，提供各种OSD功能，提供高质量图像，并且显示的图像不变形。

公开(公告)号：US07376039B2

公开(公告)日：2008-05-20

申请号：US11061903

申请日：2005-02-18

Applicant: Jin-Hyeok Choi ,  Sam-Yong Bahng

Inventor： Jin-Hyeok Choi ,  Sam-Yong Bahng

IPC: G11C5/14

CPC classification number: G11C29/32

Abstract: A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semiconductor device, and reduce power consumption in a standby state.

Abstract translation: 数据存储电路和数据保存方法，用于在半导体器件使用测试扫描链处于睡眠模式时保存数据，其中数据存储电路包括睡眠模式控制单元和扫描链单元，睡眠模式控制 响应于从外部接收的测试控制信号和睡眠模式控制信号中的一个输出扫描控制信号和扫描时钟信号，当接收到输出数据信号时，将输出数据信号存储在存储器中，并输出 测试图形数据信号作为扫描数据信号，当接收到测试图形数据信号时，扫描链单元将存储在扫描链单元内的正常数据信号作为输出数据信号输出到睡眠模式控制单元，或者接收并输出 根据扫描控制信号和扫描时钟信号将数据信号扫描到组合电路单元，数据存储电路和数据保存方法防止数据丢失为 半通道模式，并且在待机状态下降低功耗。

公开(公告)号：US20070108300A1

公开(公告)日：2007-05-17

申请号：US11650667

申请日：2007-01-08

Applicant: Chang-il Son ,  Sam-yong Bahng ,  Jong-keun Ahn ,  Sang-wook Kang

Inventor： Chang-il Son ,  Sam-yong Bahng ,  Jong-keun Ahn ,  Sang-wook Kang

IPC: G06K19/06

CPC classification number: G06K19/07732 ,  G06K19/077 ,  G06K19/07733

Abstract: A removable memory card can include a plurality of connector contacts including a Universal Serial Bus (USB) controller module power contact and a separate controller module power contact configured to provide separate mutually exclusively applied voltage to the removable memory card.

Abstract translation: 可拆卸存储卡可以包括多个连接器触点，其包括通用串行总线（USB）控制器模块电源触点和被配置为向可移动存储卡提供单独的互斥电压的单独的控制器模块电源触点。

公开(公告)号：US20050152202A1

公开(公告)日：2005-07-14

申请号：US10981367

申请日：2004-11-04

Applicant: Jin-Hyeok Choi ,  Sam-Yong Bahng ,  Chil-Hee Chung

Inventor： Jin-Hyeok Choi ,  Sam-Yong Bahng ,  Chil-Hee Chung

IPC: G11C5/14 ,  G11C7/00 ,  G11C16/30

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A memory card comprises a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.

Abstract translation: 存储卡包括非易失性存储器和用于接收外部电源电压以向非易失性存储器提供工作电压的电源管理单元，其中当外部电源电压低于检测电压时，电源管理单元提升 外部电源电压并将升压电压输出为非易失性存储器的工作电压。

公开(公告)号：US20070124558A1

公开(公告)日：2007-05-31

申请号：US11418559

申请日：2006-05-05

Applicant: Chang-Duck Lee ,  Sam-Yong Bahng ,  Sin-Ho Yang ,  Kui-Yon Mun

Inventor： Chang-Duck Lee ,  Sam-Yong Bahng ,  Sin-Ho Yang ,  Kui-Yon Mun

IPC: G06F13/00

CPC classification number: G06F13/4243 ,  G06F13/362 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal

Abstract translation: 一种用于控制与存储器件的数据交换的设备包括：接口，被配置为接收指示何时该设备使用共享总线的仲裁信号;以及与该存储器件的接口，该接口被配置为向存储器件提供同步数据交换的时钟信号 在设备和存储设备之间。 选择电路响应于仲裁信号选择性地将时钟信号提供给存储器件