-
公开(公告)号：US20120162189A1
公开(公告)日：2012-06-28
申请号：US13412258
申请日：2012-03-05
CPC分类号： H03K19/018514 , H03K19/00361 , H04L25/0276
摘要： In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.
摘要翻译： 在传输系统的驱动电路中，输出电路基于输入数据信号输出差分信号。 电流源控制电路控制恒流源，使得差分信号的共模电位变得等于预定的参考电位。 过冲减少电路连接到电流源控制电路的共模电位的输入线，并且基于控制信号减小共模电位的过冲。
-
公开(公告)号：US08265195B2
公开(公告)日：2012-09-11
申请号：US13242962
申请日：2011-09-23
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu
CPC分类号： H04L25/028 , H03K3/0322 , H03K5/15093 , H03L7/081 , H03L7/0995 , H03L2207/06 , H03M9/00 , H04L7/0337 , H04L25/0272
摘要： A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.
摘要翻译： 具有并行到串行转换功能的数据发射机由PLL电路单元提供时钟。 在PLL电路单元中，提供给第一并行转换电路的第一多相时钟由多相VCO电路产生并输出，同时产生提供给第二并行 - 串行转换电路的第二多相时钟， 由多相时钟发生器输出。 多相时钟发生器基于来自多相VCO电路的时钟输出产生第二多相时钟。
-
公开(公告)号：US20100321069A1
公开(公告)日：2010-12-23
申请号：US12526227
申请日：2007-07-23
IPC分类号： H03K3/00
CPC分类号： H04L25/0266 , H04L25/0272
摘要： A differential driver (101) includes a pair of output terminals connected to a pair of signal lines (102A and 102B), wherein in a data transmission operation, the differential driver (101) converts transmit data (TXD) to a differential signal to output the differential signal. A differential receiver includes a pair of input terminals connected to the pair of signal lines (102A and 102B), wherein in a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data (RXD). A potential setting section (106) sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines (102A and 102B).
摘要翻译： 差分驱动器（101）包括连接到一对信号线（102A和102B）的一对输出端子，其中在数据传输操作中，差分驱动器（101）将发送数据（TXD）转换为差分信号以输出 差分信号。 差分接收器包括连接到该对信号线（102A和102B）的一对输入端，其中在数据接收操作中，差分接收器接收传送到该对信号线的差分信号，并将差分信号转换成接收 数据（RXD）。 电位设定部（106）将差分信号传送到信号线对（102A，102B）之前，将一对信号线的电位设定为规定的稳定电位。
-
公开(公告)号：US20100127739A1
公开(公告)日：2010-05-27
申请号：US12595008
申请日：2008-03-18
IPC分类号： H03L7/08
CPC分类号： H03L7/197 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976
摘要： A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).
摘要翻译： 校准电路（19）调整环路滤波器电路（13）中的电荷泵电路（12）的充电电流和滤波电容器的电容值中的至少一个以及压控振荡器（14）的增益中的至少一个 ），取决于输入到校准电路（10）的参考时钟信号的频率。
-
公开(公告)号：US08035424B2
公开(公告)日：2011-10-11
申请号：US12526227
申请日：2007-07-23
IPC分类号： H03B1/00
CPC分类号： H04L25/0266 , H04L25/0272
摘要： An AC-coupled interface circuit on a semiconductor integrated circuit apparatus performing a bidirectional data transfer via a differential transmission line includes a differential driver, a differential receiver and a potential setting section. The differential driver includes a pair of output terminals connected to a pair of signal lines. The differential receiver includes a pair of input terminals connected to the pair of signal lines. In a data transmission operation, the differential driver converts transmit data to a differential signal to output the differential signal. In a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data. The potential setting section sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines.
摘要翻译： 通过差分传输线执行双向数据传输的半导体集成电路装置上的AC耦合接口电路包括差分驱动器，差分接收器和电位设定部分。 差分驱动器包括连接到一对信号线的一对输出端子。 差分接收器包括连接到该对信号线的一对输入端子。 在数据传输操作中，差分驱动器将发送数据转换为差分信号以输出差分信号。 在数据接收操作中，差分接收器接收传送到该对信号线的差分信号，并将差分信号转换为接收数据。 电位设定部分将差分信号传送到一对信号线之前，将该对信号线的电位设定为预定的稳定电位。
-
公开(公告)号：US07986175B2
公开(公告)日：2011-07-26
申请号：US12595008
申请日：2008-03-18
IPC分类号： H03L7/06
CPC分类号： H03L7/197 , H03L7/0898 , H03L7/093 , H03L7/0995 , H03L7/1976
摘要： A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).
摘要翻译： 校准电路（19）调整环路滤波器电路（13）中的电荷泵电路（12）的充电电流和滤波电容器的电容值中的至少一个以及压控振荡器（14）的增益中的至少一个 ），取决于输入到校准电路（10）的参考时钟信号的频率。
-
公开(公告)号：US20110164693A1
公开(公告)日：2011-07-07
申请号：US13047337
申请日：2011-03-14
申请人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
发明人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , G06F1/12 , H04L5/1469 , H04L5/16 , H04L25/0272 , H04L25/0298
摘要： An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.
摘要翻译： 一种在主机（1）中包括LSI（10）的接口电路和分装置（2）中的LSI（20）。 LSI（10）根据第一参考时钟信号（RFC1）分别产生第一传输时钟信号（TC1）和第一接收时钟信号（RC1）。 LSI（10）还为子设备（2）生成第二参考时钟信号（RFC2）。 参考时钟信号（RFC2）被转换为差分时钟信号，然后发送到子设备（2）。 子装置（2）的LSI（20）根据从差分时钟信号转换的第三参考时钟信号（RFC3）分别产生第二传输时钟信号（TC2）和第二接收时钟信号（RC2）。
-
公开(公告)号：US20080315911A1
公开(公告)日：2008-12-25
申请号：US12081154
申请日：2008-04-11
申请人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
发明人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
IPC分类号： H03K19/007
CPC分类号： H04L25/493
摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。
-
公开(公告)号：US07016423B2
公开(公告)日：2006-03-21
申请号：US10058904
申请日：2002-01-30
CPC分类号： H04L25/029 , H04L25/0276
摘要： The driver circuit of the present invention includes: a drive section for generating a differential signal according to an input signal and outputting the signal to an electric cable or an optical transceiver; and a control section receiving a selection signal based on which the drive section selects to drive the electric cable or the optical transceiver, an identification signal, and a data signal, for generating a signal based on the received signals and outputting the generated signal to the drive section. During a period indicated by the identification signal, the control section controls the drive section to put the output of the drive section in a high impedance state when the selection signal indicates selection of the electric cable, or output a predetermined differential signal, not putting the output in a high impedance state, when the selection signal indicates selection of the optical transceiver.
-
公开(公告)号：US06853223B2
公开(公告)日：2005-02-08
申请号：US10345994
申请日：2003-01-17
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Toru Iwata
CPC分类号： H03D13/004 , H04L7/033
摘要： The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.
摘要翻译： 本发明的目的在于提供一种相位比较器和时钟恢复电路，适用于支持高速比特速率为每秒千兆位的数据信号的应用。 相位比较器分别接收从数据信号RD / NRD产生的分频信号NHOLDH和NHOLDL，并间歇地执行信号dDAT和信号CLK之间的相位比较。 这增加了相位比较的定时裕度，并且可以对高速比特率信号执行相位比较。 提供用作时钟恢复电路的相位比较器使得可以以高达1吉比特每秒的高速比特率来处理数据信号。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.02 秒)
