公开(公告)号：US4689502A

公开(公告)日：1987-08-25

申请号：US938342

申请日：1986-12-03

申请人： Yoshiki Shimauchi ,  Katsuji Hirochi

发明人： Yoshiki Shimauchi ,  Katsuji Hirochi

IPC分类号： H01L27/082 ,  H01L21/82 ,  H01L21/8222 ,  H01L27/118 ,  H03K5/02 ,  H03K19/082 ,  H03K19/088 ,  H03K19/173 ,  H03K19/177 ,  H03K19/013 ,  H03K17/04 ,  H03K19/092

CPC分类号： H03K19/1778 ,  H01L27/11801 ,  H03K19/082 ,  H03K19/088 ,  H03K19/17796 ,  H03K5/02

摘要： A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the base thereof, a first NPN-type transistor whose base is connected to the emitters of the PNP-type transistors, and an output buffer circuit. The output buffer circuit includes a second NPN-type transistor, which is controlled by the signal at the emitter of the first NPN-type transistor and outputs electric charges from an output terminal, and a third NPN-type transistor, which is controlled by the signal at the collector of the first NPN-type transistor and which is connected in series with the second NPN-type transistor so as to supply a charging current to the output terminal.

摘要翻译： 具有内部门电路的门阵列LSI器件，其性能不受负载条件的影响并具有较大的扇出数。 内门电路包括一个或多个PNP型晶体管，每个PNP型晶体管中的每一个在其基极处接收输入信号，其基极连接到PNP型晶体管的发射极的第一NPN型晶体管，以及输出缓冲电路 。 输出缓冲电路包括第二NPN型晶体管，其由第一NPN型晶体管的发射极处的信号控制，并输出来自输出端子的电荷，第三NPN型晶体管由第三NPN型晶体管控制， 信号在第一NPN型晶体管的集电极处并与第二NPN型晶体管串联连接，以向输出端提供充电电流。

公开(公告)号：US4567380A

公开(公告)日：1986-01-28

申请号：US507496

申请日：1983-06-24

申请人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

发明人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

IPC分类号： H03K3/2893 ,  H03K3/295

CPC分类号： H03K3/2893

摘要： A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.

摘要翻译： 电平移动元件连接在用于在输入电压下降时确定阈值电平的晶体管（Tr5）和将二极管（D3）连接在输入端子和输出控制晶体管（Tr2）之间以将基极 输出控制晶体管。 电平移动元件包括在正向连接的二极管或电阻器。

公开(公告)号：US5138196A

公开(公告)日：1992-08-11

申请号：US701810

申请日：1991-05-19

申请人： Shinzou Satou ,  Yoshiki Shimauchi

发明人： Shinzou Satou ,  Yoshiki Shimauchi

IPC分类号： H03K19/0175 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/017527

摘要： A semiconductor integrated circuit has an output circuit which includes a Bi-CMOS circuit of receiving an input signal, and an ECL circuit. The ECL circuit includes a differential pair for receiving an output of the Bi-CMOS circuit, na an emitter follower for receiving an output of the differentail pair. The Bi-CMOS circuit comprises a CMOS inverter connected in series between power sources; a first npn transistor, a diode, and a second npn transistor which are connected in series between the power sources; and second and third n-channel MOS transistors for turning the second npn transistor ON and OFF. This semiconductor integrated circuit provides a stable, operation and low power consumption.

摘要翻译： 半导体集成电路具有包括接收输入信号的Bi-CMOS电路和ECL电路的输出电路。 ECL电路包括用于接收Bi-CMOS电路的输出的差分对，用于接收不同对的输出的射极跟随器。 Bi-CMOS电路包括在电源之间串联连接的CMOS反相器; 在电源之间串联连接的第一npn晶体管，二极管和第二npn晶体管; 以及用于使第二npn晶体管导通和截止的第二和第三n沟道MOS晶体管。 该半导体集成电路提供稳定，操作和低功耗。

公开(公告)号：US4888623A

公开(公告)日：1989-12-19

申请号：US256259

申请日：1988-10-12

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiki Shimauchi ,  Akinori Tahara

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiki Shimauchi ,  Akinori Tahara

IPC分类号： H01L21/74 ,  H01L21/822 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

CPC分类号： H01L21/74 ,  H01L21/743 ,  H01L27/0248

摘要： Electrostatical breakage of a semiconductor device, including an epitaxial layer and a buried layer thereunder, connected to an outer signal terminal, can be prevented by forming an impurity region in the epitaxial layer so as to form a PN junction between the buried layer and the impurity region. The impurity region is connected to a power source or ground.

摘要翻译： 可以通过在外延层中形成杂质区域来形成掩埋层和杂质之间的PN结，来防止连接到外部信号端子的包括其外部的外延层和掩埋层的半导体器件的静电破损 地区。 杂质区域连接到电源或接地。