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15 条记录 (耗时 0.024 秒)

    Schmitt trigger circuit
    1.
    发明授权
    Schmitt trigger circuit 失效
    施密特触发电路

    公开(公告)号：US4567380A

    公开(公告)日：1986-01-28

    申请号：US507496

    申请日：1983-06-24

    申请人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

    发明人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

    IPC分类号： H03K3/2893 ,  H03K3/295

    CPC分类号： H03K3/2893

    摘要： A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.

    摘要翻译： 电平移动元件连接在用于在输入电压下降时确定阈值电平的晶体管（Tr5）和将二极管（D3）连接在输入端子和输出控制晶体管（Tr2）之间以将基极 输出控制晶体管。 电平移动元件包括在正向连接的二极管或电阻器。

    Logic circuit
    3.
    发明授权
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US4774620A

    公开(公告)日：1988-09-27

    申请号：US98768

    申请日：1987-09-17

    申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

    发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

    IPC分类号： H03K19/088 ,  H03K17/082 ,  H03K17/60 ,  H03K19/003 ,  H02H3/20

    CPC分类号： H03K19/00307 ,  H03K17/0826

    摘要： A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.

    摘要翻译： 一种逻辑电路，当向电源线施加高电压并且确保高电压电阻时，减小输出级中的下拉晶体管和上拉晶体管的击穿的发生。 所述逻辑电路控制设置在第一电源和输出端之间的上拉晶体管，所述上拉晶体管根据分相晶体管的集电极电压而导通和截止，并控制所述第二电源和输出端之间提供的下拉晶体管 端子具有发射极电压。 可以减小下拉和上拉晶体管的故障，并通过提供一个保护电路来确保高电压电阻，该保护电路对下拉晶体管的基极进行放电，并通过检测下拉晶体管的电压差 第一电源和第二电源超过规定值。

    Two-stage gate circuit providing inverted and non-inverted outputs
    4.
    发明授权
    Two-stage gate circuit providing inverted and non-inverted outputs 失效
    提供反相和非反相输出的两级门电路

    公开(公告)号：US4703202A

    公开(公告)日：1987-10-27

    申请号：US700413

    申请日：1985-02-11

    申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

    发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

    IPC分类号： G06F13/14 ,  G06F7/00 ,  H03K3/286 ,  H03K3/356 ,  H03K5/04 ,  H03K5/151 ,  H03K19/003 ,  H03K19/013 ,  H03K19/088

    CPC分类号： H03K19/00307 ,  H03K19/00353 ,  H03K19/013 ,  H03K5/151

    摘要： A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.

    摘要翻译： 一种用于控制微机系统中的接口电路的门电路，包括连接在第一级门电路和第二级门电路之间的第一级门电路，二级门电路和控制装置。 第一级门电路向接口电路输出反相选通信号，第二级门电路向接口电路输出非反相选通信号。 尽管这些选通信号的转换定时存在时间滞后，但是通过连接第一级门电路和第二级门电路之间的二极管来减小该时滞。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4680600A

    公开(公告)日：1987-07-14

    申请号：US921811

    申请日：1986-10-21

    申请人： Akinori Tahara ,  Hiromu Enomoto ,  Yasushi Yasuda

    发明人： Akinori Tahara ,  Hiromu Enomoto ,  Yasushi Yasuda

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L29/861 ,  H03K19/003 ,  H01L29/56 ,  H01L29/90

    CPC分类号： H01L27/0248 ,  H03K19/00307

    摘要： A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region. The reverse withstand voltage of the PN junction type protection diode is smaller than that of the clamp diode, thereby preventing excessive reverse current flow and avoiding permanent destruction of the clamp diode.

    摘要翻译： 诸如TTL型集成电路器件的半导体器件，其具有用于每个内部电路的输入保护电路，例如每个TT逻辑门。 输入保护电路形成在第一导电类型的半导体衬底上，并且包括具有连接到外部端子的第二导电类型的第一杂质区域和在由具有第一导电类型的隔离区域包围的半导体衬底上形成的岛状 导电类型。 该器件还包括形成在与第一杂质区接触的电极层上的钳位二极管。 该器件还包括形成在具有第一导电类型的第二杂质区上的PN结型保护二极管; 保护二极管穿过钳位二极管与连接到外部端子的第一杂质区域的一部分之间的第一杂质区域并到达隔离区域。 PN结型保护二极管的反向耐压小于钳位二极管的反向耐压，从而防止过大的反向电流流动，并避免钳位二极管的永久性破坏。

    Structure for and method of manufacturing a semiconductor device by the master slice method
    7.
    发明授权
    Structure for and method of manufacturing a semiconductor device by the master slice method 失效
    通过主切片方法制造半导体器件的结构和方法

    公开(公告)号：US4388755A

    公开(公告)日：1983-06-21

    申请号：US207737

    申请日：1980-11-17

    申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

    发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiharu Mitono ,  Taketo Imaizumi ,  Hitoshi Ohmichi

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/52 ,  H01L27/04 ,  H01L27/082 ,  H01L27/118 ,  H01L29/08

    CPC分类号： H01L23/52 ,  H01L27/11801 ,  H01L29/0813 ,  H01L2924/0002

    摘要： A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.

    摘要翻译： 通过主切片方法制造半导体器件的结构和方法，其中通过利用公共主图和多种不同种类的选择性布线图来制造各种半导体器件。 每个具有多个发射极区域的多个双极晶体管通过采用公共主图案形成在半导体衬底的预定区域或部分中，并且各个双极晶体管的多个发射极区域通过相关布线图案选择性地连接 以形成具有不同的预定DC特性的相应双极晶体管。 当通过主分片方法制造许多不同种类的半导体器件时，通过现有技术将浪费在半导体衬底上的区域大大减少，从而提供增强的面积效率。

    Schmitt trigger circuit with low input current
    8.
    发明授权
    Schmitt trigger circuit with low input current 失效
    施密特触发电路具有低输入电流

    公开(公告)号：US4409495A

    公开(公告)日：1983-10-11

    申请号：US268643

    申请日：1981-05-29

    申请人： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

    发明人： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

    IPC分类号： H03K3/2893 ,  H03K5/08 ,  H03K3/295

    CPC分类号： H03K3/2893

    摘要： A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

    摘要翻译： 施密特触发电路具有降低噪声灵敏度和防止振荡的输入电压滞后特性。 在其输入级具有多发射极晶体管，并且在其输出级中具有第二晶体管。 多发射极晶体管包括第一发射极和第二发射极。 响应于施加到多发射极晶体管的基极的输入电压，第一发射极与开关操作相关联。 第二发射极与从第二晶体管的基极通过多发射极晶体管的基极到地的绘制电荷的操作相关联。 使用多发射极晶体管可防止输入电流随着输入电压的下降而大幅度增加。