公开(公告)号：US20070224756A1

公开(公告)日：2007-09-27

申请号：US11456856

申请日：2006-07-11

Applicant: Yu-Pi Lee ,  Shian-Jyh Lin

Inventor： Yu-Pi Lee ,  Shian-Jyh Lin

IPC: H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10861 ,  H01L29/4236 ,  H01L29/66621

Abstract: A method of fabricating self-aligned gate trench utilizing TTO spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Spacers are formed on the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Abstract translation: 公开了一种使用TTO间隔件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 沟槽电容器形成在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 在挤出TTO上形成间隔物，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US06703311B2

公开(公告)日：2004-03-09

申请号：US10163240

申请日：2002-06-04

Applicant: Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang ,  Yu-Pi Lee

Inventor： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang ,  Yu-Pi Lee

IPC: H01L21302

CPC classification number: H01L27/10861 ,  G01R31/275 ,  H01L22/34

Abstract: A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.

Abstract translation: 一种用于估计衬底中的深沟槽电容器的电容的方法。 在用于限定下电极的区域的光致抗蚀剂层形成在掺杂有导电型掺杂剂的氧化物层上之后，测量存储单元阵列区域和支撑区域之间的光致抗蚀剂层的高度差。 高度差的根数与沟槽中要形成的电容器的电容成正比。

公开(公告)号：US20090008692A1

公开(公告)日：2009-01-08

申请号：US11966891

申请日：2007-12-28

Applicant: Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract translation: 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US20080318388A1

公开(公告)日：2008-12-25

申请号：US11955405

申请日：2007-12-13

Applicant: Shian-Jyh Lin ,  Yu-Pi Lee ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yu-Pi Lee ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC: H01L21/20

CPC classification number: H01L29/66621 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of the trench top oxide; forming a second spacer on the first spacer; defining a plurality of active areas, wherein each of the active areas is parallel with each other and comprises at least two of the trench capacitors; forming an isolation area between each of the active area; etching the substrate of the active area by using the second spacer as a mask to form a trench in the active area; removing the second spacer to expose a portion of the substrate, and etching the exposed substrate to enlarge the trench; and forming a gate structure in the trench.

Abstract translation: 一种用于制造具有凹槽通道的MOS晶体管的方法，包括：在其中为衬底提供多个沟槽电容器，其中沟槽顶部氧化物位于每个沟槽电容器的顶部并且远离衬底表面延伸; 在所述沟槽顶部氧化物的侧壁上形成第一间隔物; 在所述第一间隔物上形成第二间隔物; 限定多个有效区域，其中每个有源区域彼此平行并且包括至少两个沟槽电容器; 在每个所述活动区域之间形成隔离区域; 通过使用第二间隔件作为掩模蚀刻有源区的衬底，以在有源区中形成沟槽; 去除所述第二间隔物以暴露所述衬底的一部分，并蚀刻所述暴露的衬底以扩大所述沟槽; 并在沟槽中形成栅极结构。

公开(公告)号：US07955927B2

公开(公告)日：2011-06-07

申请号：US11966891

申请日：2007-12-28

Applicant: Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC: H01L21/8242

CPC classification number: H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract translation: 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US20070264788A1

公开(公告)日：2007-11-15

申请号：US11431588

申请日：2006-05-11

Applicant: Yu-Pi Lee ,  Shian-Jyh Lin

Inventor： Yu-Pi Lee ,  Shian-Jyh Lin

IPC: H01L21/20

CPC classification number: H01L29/66621 ,  H01L21/26586 ,  H01L27/10838 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned layer of silicon nitride over the substrate so that at the location where the two trench capacitors are desired to be built, the substrate is exposed; then to build the two trench capacitors at the location of the exposed substrate. Form a layer of silicon oxide to cover the capacitors and make the layer of silicon oxide and the layer of silicon nitride at the same level. Layer of silicon nitride is removed afterwards, and a polysilicon layer is conformably formed on the substrate. A BF2 ion implantation is performed twice at different tilt angles on the polysilicon layer in order to define an undoped area between the two trench capacitors. Then remove the undoped area of the polysilicon layer so that part of the silicon substrate is exposed to serve as the predetermined location of transistor gate.

Abstract translation: 确定动态随机存取存储器（DRAM）的晶体管栅极的预定位置的方法。 沟槽电容器分别在栅极的两侧沿着位线的方向设置在硅衬底中。 该方法是首先在衬底上形成图案化的氮化硅层，使得在需要构建两个沟槽电容器的位置处，衬底被暴露; 然后在暴露的基板的位置处构建两个沟槽电容器。 形成一层氧化硅以覆盖电容器，并使氧化硅层和氮化硅层处于同一水平。 之后去除氮化硅层，并且在衬底上顺应地形成多晶硅层。 在多晶硅层上以不同的倾斜角进行两次BF2离子注入，以便限定两个沟槽电容器之间的未掺杂区域。 然后去除多晶硅层的未掺杂区域，使得硅衬底的一部分暴露以用作晶体管栅极的预定位置。

公开(公告)号：US20070155179A1

公开(公告)日：2007-07-05

申请号：US11456207

申请日：2006-07-09

Applicant: Jar-Ming Ho ,  Shian-Jyh Lin ,  Yu-Pi Lee

Inventor： Jar-Ming Ho ,  Shian-Jyh Lin ,  Yu-Pi Lee

IPC: H01L21/311 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/302

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L27/1087

Abstract: The present invention provides a method for fabricating a trench opening in a semiconductor substrate. The patterned amorphous silicon layer is completely oxidized to form a silicon oxide mask having openings with shrunk critical dimensions. The silicon oxide mask is used as an etching hard mask in the subsequent trench etching process. The present invention is not only suited for the fabrication of trench-capacitor DRAM devices, but also suited for the semiconductor contact/via processes.

Abstract translation: 本发明提供一种在半导体衬底中制造沟槽开口的方法。 图案化的非晶硅层被完全氧化以形成具有收缩临界尺寸的开口的氧化硅掩模。 在随后的沟槽蚀刻工艺中，氧化硅掩模用作蚀刻硬掩模。 本发明不仅适用于制造沟槽电容器DRAM器件，而且也适用于半导体接触/通孔工艺。

公开(公告)号：US20070264772A1

公开(公告)日：2007-11-15

申请号：US11685756

申请日：2007-03-13

Applicant: Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

Inventor： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

IPC: H01L21/8242

CPC classification number: H01L29/66621 ,  H01L21/26586 ,  H01L21/28061 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66545

Abstract: A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Abstract translation: 公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US07588984B2

公开(公告)日：2009-09-15

申请号：US11431588

申请日：2006-05-11

Applicant: Yu-Pi Lee ,  Shian-Jyh Lin

Inventor： Yu-Pi Lee ,  Shian-Jyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/26586 ,  H01L27/10838 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned layer of silicon nitride over the substrate so that at the location where the two trench capacitors are desired to be built, the substrate is exposed; then to build the two trench capacitors at the location of the exposed substrate. Form a layer of silicon oxide to cover the capacitors and make the layer of silicon oxide and the layer of silicon nitride at the same level. Layer of silicon nitride is removed afterwards, and a polysilicon layer is conformably formed on the substrate. A BF2 ion implantation is performed twice at different tilt angles on the polysilicon layer in order to define an undoped area between the two trench capacitors. Then remove the undoped area of the polysilicon layer so that part of the silicon substrate is exposed to serve as the predetermined location of transistor gate.

Abstract translation: 确定动态随机存取存储器（DRAM）的晶体管栅极的预定位置的方法。 沟槽电容器沿着位线的方向在栅极的两侧分别设置在硅衬底中。 该方法是首先在衬底上形成图案化的氮化硅层，使得在需要构建两个沟槽电容器的位置处，衬底被暴露; 然后在暴露的基板的位置处构建两个沟槽电容器。 形成一层氧化硅以覆盖电容器，并使氧化硅层和氮化硅层处于同一水平。 之后去除氮化硅层，并且在衬底上顺应地形成多晶硅层。 在多晶硅层上以不同的倾斜角进行两次BF2离子注入，以便限定两个沟槽电容器之间的未掺杂区域。 然后去除多晶硅层的未掺杂区域，使得硅衬底的一部分暴露以用作晶体管栅极的预定位置。

公开(公告)号：US07510930B2

公开(公告)日：2009-03-31

申请号：US11685756

申请日：2007-03-13

Applicant: Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

Inventor： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

IPC: H01L21/8242

CPC classification number: H01L29/66621 ,  H01L21/26586 ,  H01L21/28061 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66545

Abstract: A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Abstract translation: 公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。