公开(公告)号：US20090008692A1

公开(公告)日：2009-01-08

申请号：US11966891

申请日：2007-12-28

申请人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

发明人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10894

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US07955927B2

公开(公告)日：2011-06-07

申请号：US11966891

申请日：2007-12-28

申请人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

发明人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10894

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US20080318388A1

公开(公告)日：2008-12-25

申请号：US11955405

申请日：2007-12-13

申请人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

发明人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC分类号： H01L21/20

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7854

摘要： A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of the trench top oxide; forming a second spacer on the first spacer; defining a plurality of active areas, wherein each of the active areas is parallel with each other and comprises at least two of the trench capacitors; forming an isolation area between each of the active area; etching the substrate of the active area by using the second spacer as a mask to form a trench in the active area; removing the second spacer to expose a portion of the substrate, and etching the exposed substrate to enlarge the trench; and forming a gate structure in the trench.

摘要翻译： 一种用于制造具有凹槽通道的MOS晶体管的方法，包括：在其中为衬底提供多个沟槽电容器，其中沟槽顶部氧化物位于每个沟槽电容器的顶部并且远离衬底表面延伸; 在所述沟槽顶部氧化物的侧壁上形成第一间隔物; 在所述第一间隔物上形成第二间隔物; 限定多个有效区域，其中每个有源区域彼此平行并且包括至少两个沟槽电容器; 在每个所述活动区域之间形成隔离区域; 通过使用第二间隔件作为掩模蚀刻有源区的衬底，以在有源区中形成沟槽; 去除所述第二间隔物以暴露所述衬底的一部分，并蚀刻所述暴露的衬底以扩大所述沟槽; 并在沟槽中形成栅极结构。

公开(公告)号：US20090134442A1

公开(公告)日：2009-05-28

申请号：US12103590

申请日：2008-04-15

申请人： Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

发明人： Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10867 ,  H01L27/10876

摘要： A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided.

摘要翻译： 用于形成凹陷通道器件的方法包括：提供其上形成有多个沟槽电容器的衬底，每个沟槽电容器包括突出在衬底上方的插头; 在每个插头上形成间隔件; 在与所述沟槽电容器相邻的所述衬底中沿着第一方向形成多个沟槽隔离，以限定暴露所述衬底的有源区; 通过使用间隔物和沟槽隔离物作为掩模去除衬底的一部分以形成凹陷沟道; 并且修整凹陷通道，使得凹陷通道的表面轮廓呈现三维形状。 还提供了具有圆形通道轮廓的凹槽通道装置。

公开(公告)号：US20090068813A1

公开(公告)日：2009-03-12

申请号：US11964516

申请日：2007-12-26

申请人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

发明人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

IPC分类号： H01L21/02

CPC分类号： H01L29/945 ,  H01L23/544 ,  H01L27/1087 ,  H01L29/66181 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

摘要翻译： 一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。 在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。 在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。 在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。 在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

公开(公告)号：US07803701B2

公开(公告)日：2010-09-28

申请号：US11964516

申请日：2007-12-26

申请人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

发明人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

IPC分类号： H01L21/8242 ,  H01L21/425

CPC分类号： H01L29/945 ,  H01L23/544 ,  H01L27/1087 ,  H01L29/66181 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

摘要翻译： 一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。 在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。 在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。 在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。 在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

公开(公告)号：US07510930B2

公开(公告)日：2009-03-31

申请号：US11685756

申请日：2007-03-13

申请人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

发明人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L21/28061 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66545

摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US20070264772A1

公开(公告)日：2007-11-15

申请号：US11685756

申请日：2007-03-13

申请人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

发明人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L21/28061 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66545

摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US20070155179A1

公开(公告)日：2007-07-05

申请号：US11456207

申请日：2006-07-09

申请人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Yu-Pi Lee

发明人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Yu-Pi Lee

IPC分类号： H01L21/311 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/1087

摘要： The present invention provides a method for fabricating a trench opening in a semiconductor substrate. The patterned amorphous silicon layer is completely oxidized to form a silicon oxide mask having openings with shrunk critical dimensions. The silicon oxide mask is used as an etching hard mask in the subsequent trench etching process. The present invention is not only suited for the fabrication of trench-capacitor DRAM devices, but also suited for the semiconductor contact/via processes.

摘要翻译： 本发明提供一种在半导体衬底中制造沟槽开口的方法。 图案化的非晶硅层被完全氧化以形成具有收缩临界尺寸的开口的氧化硅掩模。 在随后的沟槽蚀刻工艺中，氧化硅掩模用作蚀刻硬掩模。 本发明不仅适用于制造沟槽电容器DRAM器件，而且也适用于半导体接触/通孔工艺。

公开(公告)号：US07622381B2

公开(公告)日：2009-11-24

申请号：US11829371

申请日：2007-07-27

申请人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

发明人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L27/10888 ,  H01L27/10894

摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.

摘要翻译： 本发明提供一种半导体结构及其形成方法。 该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。 此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。