公开(公告)号：US20050250273A1

公开(公告)日：2005-11-10

申请号：US11180658

申请日：2005-07-14

申请人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

发明人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

IPC分类号： G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L23/52 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L21/28568 ,  G03G15/0131 ,  G03G15/1685 ,  G03G2215/0141 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78603

摘要： The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is used in a source/drain electrode and a barrier layer made of molybdenum or a molybdenum alloy layer is formed between the aluminum-based conductive layer and a polysilicon layer. Further, a molybdenum oxide nitride film formed by the rapid heat treatment (rapid heat annealing) in a nitrogen atmosphere is formed over a surface of the molybdenum or the molybdenum alloy which constitutes the barrier layer.

公开(公告)号：US20050249525A1

公开(公告)日：2005-11-10

申请号：US11180358

申请日：2005-07-13

申请人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

发明人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

IPC分类号： G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L23/52 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  G03G15/01

CPC分类号： H01L21/28568 ,  G03G15/0131 ,  G03G15/1685 ,  G03G2215/0141 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78603

摘要： An endless belt transports a recording medium through image forming sections and transfers toner images from corresponding ones of the image forming sections onto the recording medium. The endless belt has a surface resistivity and a volume resistivity. The surface resistivity and the volume resistivity are related such that 0.3 ≦(log ρ s−log ρ v)≦1.3 where ρ s is the surface resistivity in Ω/□ measured after a voltage of substantially 500 V is applied to the endless belt for ten seconds and ρ v is the volume resistivity in Ω·cm ten after a voltage of substantially 250 V is applied to the endless belt for ten seconds.

摘要翻译： 环形带通过图像形成部分传送记录介质，并将调色剂图像从对应的图像形成部分转印到记录介质上。 环形带具有表面电阻率和体积电阻率。 表面电阻率和体积电阻率相关，使得0.3 <=（log rho s-log rho v）<= 1.3其中rho是在基本上500V的电压之后测量的以Ω/□表示的表面电阻率施加到环形 皮带10秒钟，rho v是在大约250V的电压施加到环形带上十秒钟之后的体积电阻率（Ω·cm·cm）。

公开(公告)号：US06433842B1

公开(公告)日：2002-08-13

申请号：US09537395

申请日：2000-03-29

申请人： Toshiki Kaneko ,  Masaru Takabatake ,  Takahiro Ochiai ,  Takuya Takahashi ,  Katsumi Tamura ,  Kenichi Onisawa ,  Kenichi Cyahara ,  Masatomo Terakado ,  Yuichi Harano ,  Hideaki Yamamoto

发明人： Toshiki Kaneko ,  Masaru Takabatake ,  Takahiro Ochiai ,  Takuya Takahashi ,  Katsumi Tamura ,  Kenichi Onisawa ,  Kenichi Cyahara ,  Masatomo Terakado ,  Yuichi Harano ,  Hideaki Yamamoto

IPC分类号： G02F1136

CPC分类号： G02F1/136286 ,  G02F2001/13629

摘要： The method of fabrication of a liquid crystal display device includes the steps of: forming a metal thin film on a glass substrate; forming a resist pattern on the metal thin film by photolithography; and wet-etching the metal thin film with an etchant formed of a mixture including phosphoric acid, nitric acid in a range between 7 mol % and 12 mol % inclusive, and at least one of ammonium fluoride and hydrogen fluoride in a trace amount of about 0.01 to 0.1 mol %.

摘要翻译： 制造液晶显示装置的方法包括以下步骤：在玻璃基板上形成金属薄膜; 通过光刻在金属薄膜上形成抗蚀剂图案; 并用由包括磷酸，硝酸在7摩尔％至12摩尔％之间的混合物的混合物形成的蚀刻剂湿蚀刻金属薄膜，以及微量约为的氟化铵和氟化氢中的至少一种 0.01〜0.1摩尔％。

公开(公告)号：US20100055879A1

公开(公告)日：2010-03-04

申请号：US12480077

申请日：2009-06-08

申请人： Yuichi HARANO ,  Hidenori SUZUKI

发明人： Yuichi HARANO ,  Hidenori SUZUKI

IPC分类号： H01L21/326

CPC分类号： H01L21/6831

摘要： A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

摘要翻译： 将晶片安装在具有静电卡盘功能的平台的顶表面上，并且将在50℃或更高的晶片冷却至低于50℃的温度。在该步骤中，施加到内部的电压 设置在台架中的电极逐步升高以逐渐增加晶片的背表面和台的顶表面之间的接触面积。 最后，向内部电极施加卡盘电压，使得晶片的整个背面被均匀地吸引到台的顶面。 这减少了由于在晶片的后表面和台的顶表面之间的摩擦而在台的顶表面中发生的损坏。

公开(公告)号：US08338272B2

公开(公告)日：2012-12-25

申请号：US12480077

申请日：2009-06-08

申请人： Yuichi Harano ,  Hidenori Suzuki

发明人： Yuichi Harano ,  Hidenori Suzuki

IPC分类号： H01L21/326

CPC分类号： H01L21/6831

摘要： A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

摘要翻译： 将晶片安装在具有静电卡盘功能的平台的顶表面上，并且将在50℃或更高的晶片冷却至低于50℃的温度。在该步骤中，施加到内部的电压 设置在台架中的电极逐步升高以逐渐增加晶片的背表面和台的顶表面之间的接触面积。 最后，向内部电极施加卡盘电压，使得晶片的整个背面被均匀地吸引到台的顶面。 这减少了由于在晶片的后表面和台的顶表面之间的摩擦而在台的顶表面中发生的损坏。

公开(公告)号：US20110127158A1

公开(公告)日：2011-06-02

申请号：US12940159

申请日：2010-11-05

申请人： Takashi HAMAYA ,  Hidenori SUZUKI ,  Yuichi HARANO ,  Masahiko ITO

发明人： Takashi HAMAYA ,  Hidenori SUZUKI ,  Yuichi HARANO ,  Masahiko ITO

IPC分类号： C23C14/34

CPC分类号： H01L21/2855 ,  C23C14/564 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： In a copper damascene wiring process, a tantalum-based laminated film, which is used as a barrier metal film, is continuously formed in a sputtering deposition chamber. When the continuous deposition process is discontinuously applied to a number of wafers, a tantalum film and a tantalum nitride film which are relatively thin are alternately deposited over an inner surface of a shield in a sputter deposition chamber, which results in a thickness of the deposited film being on the order of several thousand nanometers. The deposited film peels off due to internal stress therein to generate foreign material or particles. To counteract this, a tantalum film, which is much thicker than the tantalum film formed over the wafer at one time, is formed over the substantially inner wall of the chamber at predetermined intervals when repeatedly depositing the tantalum nitride film and the tantalum film in the sputtering deposition chamber.

摘要翻译： 在铜镶嵌布线方法中，在溅射沉积室中连续地形成用作阻挡金属膜的钽基层压膜。 当连续沉积过程不连续地施加到多个晶片时，相对薄的钽膜和氮化钽膜交替沉积在溅射沉积室中的屏蔽的内表面上，这导致沉积的厚度 大约数千纳米的电影。 沉积膜由于其中的内部应力而剥离以产生异物或颗粒。 为了抵消这种情况，当以一定间隔形成厚度大于在晶片上形成的钽膜的钽膜时，在反复沉积氮化钽膜和钽膜时，以预定间隔形成在腔的基本内壁上 溅射沉积室。

公开(公告)号：US07479451B2

公开(公告)日：2009-01-20

申请号：US11180658

申请日：2005-07-14

申请人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

发明人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

IPC分类号： H01L21/44

CPC分类号： H01L21/28568 ,  G03G15/0131 ,  G03G15/1685 ,  G03G2215/0141 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78603

摘要： The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is used in a source/drain electrode and a barrier layer made of molybdenum or a molybdenum alloy layer is formed between the aluminum-based conductive layer and a polysilicon layer. Further, a molybdenum oxide nitride film formed by the rapid heat treatment (rapid heat annealing) in a nitrogen atmosphere is formed over a surface of the molybdenum or the molybdenum alloy which constitutes the barrier layer.

摘要翻译： 本发明防止了在与低温多晶硅接触的源/漏电极中使用铝基导电层时，在加热步骤中铝元素扩散到多晶硅层中，从而可以发生不良显示 消除了 在源/漏电极中使用铝基导电层，并且在铝基导电层和多晶硅层之间形成由钼制成的阻挡层或钼合金层。 此外，在构成阻挡层的钼或钼合金的表面上形成在氮气氛中通过快速热处理（快速热退火）形成的氧化钼氮化物膜。

公开(公告)号：US06933525B2

公开(公告)日：2005-08-23

申请号：US10742896

申请日：2003-12-23

申请人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

发明人： Yuichi Harano ,  Jun Gotoh ,  Toshiki Kaneko ,  Masanao Yamamoto

IPC分类号： G02F1/1368 ,  G09F9/30 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L23/52 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/28568 ,  G03G15/0131 ,  G03G15/1685 ,  G03G2215/0141 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78603

摘要： The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is used in a source/drain electrode and a barrier layer made of molybdenum or a molybdenum alloy layer is formed between the aluminum-based conductive layer and a polysilicon layer. Further, a molybdenum oxide nitride film formed by the rapid heat treatment (rapid heat annealing) in a nitrogen atmosphere is formed over a surface of the molybdenum or the molybdenum alloy which constitutes the barrier layer.

摘要翻译： 本发明防止了在与低温多晶硅接触的源/漏电极中使用铝基导电层时，在加热步骤中铝元素扩散到多晶硅层中，从而可以发生不良显示 消除了 在源/漏电极中使用铝基导电层，并且在铝基导电层和多晶硅层之间形成由钼制成的阻挡层或钼合金层。 此外，在构成阻挡层的钼或钼合金的表面上形成在氮气氛中通过快速热处理（快速热退火）形成的氧化钼氮化物膜。