公开(公告)号：US08895400B2

公开(公告)日：2014-11-25

申请号：US13473751

申请日：2012-05-17

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L21/331 ,  H01L27/108 ,  H01L21/74 ,  H01L21/311

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US20120264280A1

公开(公告)日：2012-10-18

申请号：US13473751

申请日：2012-05-17

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L21/768

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US20080048333A1

公开(公告)日：2008-02-28

申请号：US11842416

申请日：2007-08-21

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US07619281B2

公开(公告)日：2009-11-17

申请号：US11797137

申请日：2007-05-01

申请人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L27/10826 ,  H01L27/10891 ,  H01L27/24 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7853

摘要： A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.

摘要翻译： 公开了具有具有成形栅极沟槽的掩埋栅极线的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底中以限定多表面有源区/沟道的沟槽隔离层。 延伸到沟槽隔离层的栅极线填充栅极沟槽的一部分。 栅极沟槽形成有一系列凹陷以容纳通道中的峰值。 凹陷/峰值的组合用于增加通道的有效面积，从而能够在不增加其宽度的情况下形成更小的沟道半导体器件。

公开(公告)号：US20080079070A1

公开(公告)日：2008-04-03

申请号：US11797137

申请日：2007-05-01

申请人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L27/10826 ,  H01L27/10891 ,  H01L27/24 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7853

摘要： A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.

摘要翻译： 公开了具有具有成形栅极沟槽的掩埋栅极线的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底中以限定多表面有源区/沟道的沟槽隔离层。 延伸到沟槽隔离层的栅极线填充栅极沟槽的一部分。 栅极沟槽形成有一系列凹陷以容纳通道中的峰值。 凹陷/峰值的组合用于增加通道的有效面积，从而能够在不增加其宽度的情况下形成更小的沟道半导体器件。

公开(公告)号：US20080029810A1

公开(公告)日：2008-02-07

申请号：US11563365

申请日：2006-11-27

申请人： Bong Soo Kim ,  Yun-Gi Kim ,  Hyeoung-Won Seo

发明人： Bong Soo Kim ,  Yun-Gi Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices capable of maintaining a liner on both sidewalls of an active region overlapping a gate are provided. An isolation trench defining an active region is formed in a semiconductor substrate. A liner is formed on sidewalls of the active region. An isolation layer filling the isolation trench is formed. A hard mask pattern is formed on the semiconductor substrate having the liner and the isolation layer. A gate trench crossing the active region is formed using the hard mask pattern as an etching mask. A gate is formed in the gate trench. After forming the gate, the hard mask pattern is removed. A gate capping pattern is formed on the gate.

摘要翻译： 提供了制造能够在与栅极重叠的有源区域的两侧壁上保持衬垫的半导体器件的制造方法。 在半导体衬底中形成限定有源区的隔离沟槽。 衬垫形成在活性区域的侧壁上。 形成了填充隔离沟槽的隔离层。 在具有衬垫和隔离层的半导体衬底上形成硬掩模图案。 使用硬掩模图案作为蚀刻掩模形成与有源区交叉的栅极沟槽。 栅极形成在栅极沟槽中。 在形成栅极之后，去除硬掩模图案。 栅极上形成栅极覆盖图案。

公开(公告)号：US20080003753A1

公开(公告)日：2008-01-03

申请号：US11608482

申请日：2006-12-08

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.

摘要翻译： 半导体器件包括设置在半导体器件中以限定有源区的隔离层。 栅极沟槽横跨有源区域设置并延伸到隔离层。 绝缘栅电极填充栅极沟槽的一部分并覆盖有源区的至少一个侧壁。 覆盖有源区的至少一个侧壁的栅电极的一部分在与有源区交叉的栅电极的一部分之下延伸。 绝缘图案设置在栅电极上。

公开(公告)号：US07659597B2

公开(公告)日：2010-02-09

申请号：US11675829

申请日：2007-02-16

申请人： Seong-Goo Kim ,  Yun-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

发明人： Seong-Goo Kim ,  Yun-Gi Kim ,  Jae-Man Yoon ,  Hyeoung-Won Seo

IPC分类号： H01L23/52 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/28123 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/52 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。 导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接 的金属化。 插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。 还讨论了相关的制造方法。

公开(公告)号：US07781285B2

公开(公告)日：2010-08-24

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US20100267210A1

公开(公告)日：2010-10-21

申请号：US12662393

申请日：2010-04-14

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/8239

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。