公开(公告)号：US20230120305A1

公开(公告)日：2023-04-20

申请号：US17965888

申请日：2022-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHIA-HAO CHENG ,  RAHUL AGARWAL ,  CHINTAN BUCH ,  ARSALAN ALAM

IPC: H01L21/66 ,  H01L23/48 ,  H01L23/00 ,  H01L21/463 ,  H01L21/465 ,  H01L21/3205

Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

公开(公告)号：US20240113070A1

公开(公告)日：2024-04-04

申请号：US17957483

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHINTAN BUCH ,  RAJA SWAMINATHAN

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1432 ,  H01L2924/37001

Abstract: A method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. A die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. One or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. A second wafer is coupled to a top surface of the die. An amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.