公开(公告)号：US20150121519A1

公开(公告)日：2015-04-30

申请号：US14528431

申请日：2014-10-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

IPC: G06F21/57 ,  G06F1/26 ,  G06F21/50

CPC classification number: G06F1/26 ,  G06F1/324 ,  G06F1/329 ,  G06F21/755 ,  Y02D10/126 ,  Y02D10/24

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request. The system further includes performance state security logic operative to adjust, in response to the request, an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state.

Abstract translation: 本公开涉及一种用于确保一个或多个处理器的性能状态改变的方法和系统。 所公开的方法包括检测将处理器的当前性能状态改变为目标性能状态的请求，以及调整当前性能状态的操作级别容差范围以包括与从当前执行状态到目标的转换相关联的操作级别 表现状态。 所公开的系统包括操作系统模块，其操作以发送对至少一个处理核心的性能状态改变的请求。 该系统包括性能状态控制逻辑，其可操作以基于该请求改变至少一个处理核心的性能状态。 该系统还包括可执行的性能状态安全逻辑，用于响应于该请求调整当前性能状态的操作级容限范围，以包括与从当前性能状态到目标性能状态的转换相关联的操作级别。

公开(公告)号：US09870473B2

公开(公告)日：2018-01-16

申请号：US14529278

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

IPC: H04L29/06 ,  G06F21/57 ,  G06F21/50 ,  G06F1/26 ,  G06F21/81 ,  G06F1/32

CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

公开(公告)号：US20150121520A1

公开(公告)日：2015-04-30

申请号：US14529278

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

IPC: G06F21/57 ,  G06F1/26 ,  G06F21/50

CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

Abstract translation: 本公开提供了用于控制处理器的一个或多个处理核心的功率状态（其可以包括C状态）的方法和装置。 在一方面，提出了一种确保处理器的电源状态改变的示例性方法，所述方法包括以下步骤：从处理器接收电力状态改变请求，所述处理器具有多个潜在功率状态，每个包括工作功率分布 ; 确定与所述处理器相关联的功率状态改变请求模式; 将所述电力状态改变请求转发到所述电力状态改变请求模式是一次性请求模式的安全处理器; 响应于该请求从安全处理器接收电力状态改变请求响应; 以及将所述处理器的当前功率状态调整到所述电力状态改变请求响应包括电力状态改变许可的所述目标电力状态。

公开(公告)号：US10146282B2

公开(公告)日：2018-12-04

申请号：US14528431

申请日：2014-10-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

IPC: G06F1/26 ,  G06F1/32 ,  G06F21/75

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request. The system further includes performance state security logic operative to adjust, in response to the request, an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state.

公开(公告)号：US09396360B2

公开(公告)日：2016-07-19

申请号：US13928930

申请日：2013-06-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

IPC: G06F3/00 ,  G06F21/81

CPC classification number: G06F21/81

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes intercepting a request for a change of a performance state of the processor and determining whether to execute the request based on a security condition of the processor. The performance state of the processor includes at least one of an operating voltage and an operating frequency. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic in communication with the operating system module and operative to receive the request and to change the performance state of the at least one processing core based on the request. The computing system further includes performance state security logic operative to intercept the request transmitted from the operating system module to the performance state control logic and to selectively transmit the request to the performance state control logic based on a security condition of the computing system.

Abstract translation: 本公开涉及一种用于确保一个或多个处理器的性能状态改变的方法和系统。 所公开的方法包括拦截对处理器的性能状态的改变的请求，并且基于处理器的安全条件来确定是否执行请求。 处理器的性能状态包括工作电压和工作频率中的至少一个。 所公开的系统包括操作系统模块，其操作以发送对至少一个处理核心的性能状态改变的请求。 该系统包括与操作系统模块通信的性能状态控制逻辑，并且可操作以基于该请求接收该请求并改变至少一个处理核心的性能状态。 计算系统还包括性能状态安全逻辑，其可操作地拦截从操作系统模块发送到性能状态控制逻辑的请求，并且基于计算系统的安全状况来选择性地将该请求发送到性能状态控制逻辑。

公开(公告)号：US20150007356A1

公开(公告)日：2015-01-01

申请号：US13928930

申请日：2013-06-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jonathan Hauke ,  Benjamin Tsien ,  Denis Rystsov

IPC: G06F21/81

CPC classification number: G06F21/81

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes intercepting a request for a change of a performance state of the processor and determining whether to execute the request based on a security condition of the processor. The performance state of the processor includes at least one of an operating voltage and an operating frequency. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic in communication with the operating system module and operative to receive the request and to change the performance state of the at least one processing core based on the request. The computing system further includes performance state security logic operative to intercept the request transmitted from the operating system module to the performance state control logic and to selectively transmit the request to the performance state control logic based on a security condition of the computing system.

Abstract translation: 本公开涉及一种用于确保一个或多个处理器的性能状态改变的方法和系统。 所公开的方法包括拦截对处理器的性能状态的改变的请求，并且基于处理器的安全条件来确定是否执行请求。 处理器的性能状态包括工作电压和工作频率中的至少一个。 所公开的系统包括操作系统模块，其操作以发送对至少一个处理核心的性能状态改变的请求。 该系统包括与操作系统模块通信的性能状态控制逻辑，并且可操作以基于该请求接收该请求并改变至少一个处理核心的性能状态。 计算系统还包括性能状态安全逻辑，其可操作地拦截从操作系统模块发送到性能状态控制逻辑的请求，并且基于计算系统的安全状况来选择性地将该请求发送到性能状态控制逻辑。