公开(公告)号：US10134464B1

公开(公告)日：2018-11-20

申请号：US15468704

申请日：2017-03-24

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C13/00

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US09607682B1

公开(公告)日：2017-03-28

申请号：US15083077

申请日：2016-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C11/4087 ,  G06F12/06 ,  G06F2212/1041 ,  G11C7/1006 ,  G11C8/10 ,  G11C8/12

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US10559345B1

公开(公告)日：2020-02-11

申请号：US16191356

申请日：2018-11-14

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G06F12/06 ,  G11C13/00 ,  G11C8/12 ,  G11C7/10 ,  G11C8/10

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US10187044B1

公开(公告)日：2019-01-22

申请号：US15694165

申请日：2017-09-01

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Dan Trock ,  Elad Valfer ,  Yair Armoza

IPC: H03K3/84 ,  H03K3/03 ,  G06F7/58 ,  H03K19/00 ,  G06F13/40

Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.

公开(公告)号：US09774317B1

公开(公告)日：2017-09-26

申请号：US15250574

申请日：2016-08-29

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Dan Trock ,  Elad Valfer ,  Yair Armoza

IPC: H03K3/03 ,  G06F7/58 ,  H03K3/84 ,  H03K19/00 ,  G06F13/40

CPC classification number: H03K3/84 ,  G06F7/588 ,  G06F13/4045 ,  H03K3/03 ,  H03K19/0002 ,  Y02D10/14 ,  Y02D10/151

Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.