Two-wire communication systems and applications

    公开(公告)号:US10311010B2

    公开(公告)日:2019-06-04

    申请号:US14884900

    申请日:2015-10-16

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

    PERIPHERAL DEVICE DIAGNOSTICS AND CONTROL OVER A TWO-WIRE COMMUNICATION BUS
    2.
    发明申请
    PERIPHERAL DEVICE DIAGNOSTICS AND CONTROL OVER A TWO-WIRE COMMUNICATION BUS 有权
    外部设备诊断和控制通过两条通信总线

    公开(公告)号:US20160034416A1

    公开(公告)日:2016-02-04

    申请号:US14884987

    申请日:2015-10-16

    Abstract: Disclosed herein are systems and techniques for peripheral device diagnostics and control over a two-wire communication bus. For example, in some embodiments, a slave device may include circuitry to receive a synchronization control frame from an upstream device, receive audio data from the upstream device subsequent to receipt of the synchronization control frame, provide a synchronization response frame toward the upstream device, and provide first data representative of an operational characteristic of an audio device coupled to the slave device subsequent to provision of the synchronization response frame; circuitry to derive timing information from the synchronization control frame; and circuitry to provide the audio data to the audio device, and receive, from a sensor coupled to the slave device, second data representative of the operational characteristic of the audio device.

    Abstract translation: 这里公开了用于外围设备诊断和通过双线通信总线的控制的系统和技术。 例如,在一些实施例中,从设备可以包括从上游设备接收同步控制帧的电路,在接收到同步控制帧之后从上游设备接收音频数据,向上游设备提供同步响应帧, 并且提供表示在提供所述同步响应帧之后耦合到所述从设备的音频设备的操作特性的第一数据; 从同步控制帧导出定时信息的电路; 以及用于向音频设备提供音频数据并且从耦合到从设备的传感器接收表示音频设备的操作特性的第二数据的电路。

    DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS
    3.
    发明申请
    DISTRIBUTED AUDIO COORDINATION OVER A TWO-WIRE COMMUNICATION BUS 有权
    通过双线通信总线进行分布式音频协调

    公开(公告)号:US20160034417A1

    公开(公告)日:2016-02-04

    申请号:US14884947

    申请日:2015-10-16

    Abstract: Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device.

    Abstract translation: 本文公开了用于通过双线通信总线进行分布式音频协调的系统和技术。 例如,在一些实施例中,第一从设备可以包括用于通过二线总线接收用于耦合到第二从设备的第二音频设备的同步控制帧,音频数据和动态处理器(DP)参数的电路 。 第一从设备可以包括从同步控制帧导出定时信息的电路,以及向耦合到第一从站的第一音频设备提供音频数据和DP参数(基于第二音频设备的DP参数)的电路 设备。

    Two-wire communication systems and applications

    公开(公告)号:US10649948B2

    公开(公告)日:2020-05-12

    申请号:US16427131

    申请日:2019-05-30

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

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