公开(公告)号：US09806734B1

公开(公告)日：2017-10-31

申请号：US15343361

申请日：2016-11-04

Applicant: Analog Devices Global

Inventor： Arvind Madan ,  Sandeep Monangi

IPC: H03M1/34 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/0624 ,  H03M1/46

Abstract: A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.

公开(公告)号：US09432035B2

公开(公告)日：2016-08-30

申请号：US14593078

申请日：2015-01-09

Applicant: ANALOG DEVICES GLOBAL

Inventor： Bhargav R. Vyas ,  Arvind Madan ,  Sandeep Monangi

IPC: H03M1/38 ,  H03M1/00 ,  H03M1/46 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/002 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1205 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/40 ,  H03M1/46

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract translation: 本文公开了多通道逐次逼近寄存器（SAR）模数转换器（ADC）以及用于多通道SAR模数转换的方法和系统。 示例性的多通道SAR ADC可以包括用于多个输入通道中的每一个的第一SAR ADC，以及在多个输入通道中共享的第二SAR ADC，多路复用器和残余放大器。 多路复用器可以从第一SAR ADC中的一个选择模拟残留信号，以便由第二SAR ADC进行转换。 残留放大器可以放大所选择的模拟残留信号。 第二SAR ADC，多路复用器和/或残余放大器可以在所有多个输入通道中共享。 在多通道SAR ADC包含N个输入通道的地方，第二个SAR ADC，多路复用器和/或残余放大器可以在N个输入通道的b个通道之间共享。

公开(公告)号：US20160204789A1

公开(公告)日：2016-07-14

申请号：US14593078

申请日：2015-01-09

Applicant: ANALOG DEVICES GLOBAL

Inventor： Bhargav R. Vyas ,  Arvind Madan ,  Sandeep Monangi

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/002 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1205 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/40 ,  H03M1/46

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract translation: 本文公开了多通道逐次逼近寄存器（SAR）模数转换器（ADC）以及用于多通道SAR模数转换的方法和系统。 示例性的多通道SAR ADC可以包括用于多个输入通道中的每一个的第一SAR ADC，以及在多个输入通道中共享的第二SAR ADC，多路复用器和残余放大器。 多路复用器可以从第一SAR ADC中的一个选择模拟残留信号，以便由第二SAR ADC进行转换。 残留放大器可以放大所选择的模拟残留信号。 第二SAR ADC，多路复用器和/或残余放大器可以在所有多个输入通道中共享。 在多通道SAR ADC包含N个输入通道的地方，第二个SAR ADC，多路复用器和/或残余放大器可以在N个输入通道的b个通道之间共享。

公开(公告)号：US10122376B2

公开(公告)日：2018-11-06

申请号：US15711176

申请日：2017-09-21

Applicant: Analog Devices Global

Inventor： Anoop Manissery Kalathil ,  Arvind Madan ,  Sandeep Monangi

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/14 ,  H03M1/80

Abstract: Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

公开(公告)号：US09935648B1

公开(公告)日：2018-04-03

申请号：US15692695

申请日：2017-08-31

Applicant: Analog Devices Global

Inventor： Maitrey Kamble ,  Arvind Madan ,  Sandeep Monangi

IPC: H03M1/46 ,  H03M1/80

CPC classification number: H03M1/466 ,  H03M1/462 ,  H03M1/804

Abstract: To reduce the overall reference charge needed to perform operations, analog-to-digital converters can maintain reference voltage connections of the bit trial capacitors of the digital-to-analog converter (DAC) from the end of a current conversion to just prior to the beginning of the next acquisition phase. At the start of the next acquisition phase, the bottom plates of the bit trial capacitors of the DAC can be shorted to generate a common mode voltage. As the conversion phase begins, the bottom plates of the sampling capacitors are disconnected from the input voltage and the bottom plates of each bit trial capacitor are shorted to generate input common-mode voltage. As bit trials progress, the shorts between the bottom plates of the bit trial capacitors are removed and the bit trial results are applied to the bottom plates of the bit trial capacitors.

公开(公告)号：US09548948B2

公开(公告)日：2017-01-17

申请号：US13963260

申请日：2013-08-09

Applicant: Analog Devices Global

Inventor： Gerard Mora Puchalt ,  Bhargav R. Vyas ,  Adrian W. Sherry ,  Arvind Madan

IPC: H04L12/931 ,  H03K17/00 ,  H03M1/12

CPC classification number: H04L49/405 ,  H03M1/1225 ,  H03M1/124

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract translation: 多通道系统，包括具有用于多个输入通道的输入的多路复用器，以及具有耦合到多路复用器的输入的多个输入的预充电缓冲器，以及耦合到多路复用器输出的输出。 多通道系统可以独立地存在，或者可以耦合到具有耦合到多路复用器的输出的输入的接收电路。 在一些情况下，接收电路是模数转换器。