公开(公告)号：US10574247B1

公开(公告)日：2020-02-25

申请号：US16131886

申请日：2018-09-14

Applicant: Analog Devices Global Unlimited Company

Inventor： Junbiao Ding ,  Tony Yincai Liu ,  Dennis A. Dempsey ,  John Jude O'Donnell

IPC: H03M1/36 ,  H03M1/06 ,  H03M1/14 ,  H03H7/40 ,  H03H11/30

Abstract: The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.

公开(公告)号：US10348250B2

公开(公告)日：2019-07-09

申请号：US15790793

申请日：2017-10-23

Applicant: Analog Devices Global Unlimited Company

Inventor： Dennis A. Dempsey

IPC: H03F1/26 ,  H03F1/02 ,  H03F1/42 ,  H03M1/66

Abstract: The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.

公开(公告)号：US20190123692A1

公开(公告)日：2019-04-25

申请号：US15790793

申请日：2017-10-23

Applicant: Analog Devices Global Ulimited Company

Inventor： Dennis A. Dempsey

IPC: H03F1/26 ,  H03F1/42 ,  H03F1/02 ,  H03M1/66

CPC classification number: H03F1/26 ,  H03F1/0205 ,  H03F1/42 ,  H03F2200/129 ,  H03F2200/171 ,  H03F2200/372 ,  H03M1/0626 ,  H03M1/66

Abstract: The noise power of an amplifier or buffer can increase towards the unity gain cross-over frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.

公开(公告)号：US20170047149A1

公开(公告)日：2017-02-16

申请号：US14823843

申请日：2015-08-11

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H01C13/00 ,  H03M1/66

CPC classification number: H03M1/765

Abstract: The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.

Abstract translation: 本申请一般涉及可编程阻抗，并且采用与主可编程阻抗并联的辅助阻抗，以在较低阻抗值下增加主可编程阻抗的性能。

公开(公告)号：US09407278B1

公开(公告)日：2016-08-02

申请号：US14789705

申请日：2015-07-01

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/00 ,  H03M1/68 ,  H03M1/80

CPC classification number: H03M1/66 ,  H03M1/661 ,  H03M1/68 ,  H03M1/808

Abstract: In an example, there is disclosed a digital to analog converter (DAC) architecture that in a first aspect provides first and second parallel paths through the DAC so as to allow a separation of a coarse and fine aspect of the DAC transfer function is described. In another aspect a DAC architecture is provided that comprises at an output of the DAC an interpolator arranged to extend the resolution of the overall DAC architecture by interpolating within the voltage range of the DAC stages that precede the interpolator. Such an interpolator can be used with both an amplifier and/or comparator to provide one or more of a buffering of the output and/or a comparison of the DAC output with signals from other circuit elements. Features of the first and second aspects may be used independently of one another.

Abstract translation: 在一个示例中，公开了一种数模转换器（DAC）架构，其在第一方面提供了通过DAC的第一和第二并行路径，以便分离DAC传递函数的粗略和精细方面。 在另一方面，提供一种DAC架构，其包括在DAC的输出处，内插器被布置成通过在该内插器之前的DAC级的电压范围内进行内插来扩展整个DAC体系结构的分辨率。 这样的内插器可以与放大器和/或比较器一起使用以提供输出的缓冲和/或DAC输出与来自其它电路元件的信号的比较中的一个或多个。 第一和第二方面的特征可以彼此独立地使用。

公开(公告)号：US10454493B2

公开(公告)日：2019-10-22

申请号：US15150910

申请日：2016-05-10

Applicant: Analog Devices Global

Inventor： Dennis A. Dempsey ,  Michael C. W. Coln

IPC: H03M1/06 ,  H03M1/78 ,  H01L23/34 ,  H01L49/02 ,  H03F3/45 ,  H03M1/74

Abstract: Many electronic circuits rely on the ratio of one component to other components being well defined. Current flow in component can warm the component causing its electrical properties to change, for example the resistance of a resistor may increase due to self-heating as a result of current flow. The present disclosure provides a way to reduce temperature variation between components so as to reduce electrical mismatch between them or the consequences of such mismatch. This is important as even a change of resistance of, for example, 20-50 ppm in a resistor can result in non-linearity exceeding the least significant bit value of a 16 bit digital to analog converter.

公开(公告)号：US10425098B2

公开(公告)日：2019-09-24

申请号：US15947222

申请日：2018-04-06

Applicant: Analog Devices Global

Inventor： Tony Yincai Liu ,  Dennis A. Dempsey

IPC: H03M1/80 ,  H03M1/78 ,  H03M1/08 ,  H03M1/70 ,  G05D3/14 ,  H03M1/68 ,  H03M1/10 ,  H03M1/76

Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

公开(公告)号：US20180321187A1

公开(公告)日：2018-11-08

申请号：US15586942

申请日：2017-05-04

Applicant: Analog Devices Global

Inventor： Shurong Gu ,  Hanqing Wang ,  GuangYang Qu ,  Dennis A. Dempsey

IPC: G01N27/416 ,  G01N27/48

CPC classification number: G01N27/4163 ,  G01N27/416

Abstract: Techniques for generating a diagnostic waveform for a sensor are provided. In an example, a control circuit for an electrochemical sensor can include power supply inputs configured to receive a supply voltage, a first signal generator configured to receive control information and to generate a first signal on a first output using the supply voltage and the control information, a second signal generator configured to receive the control information and to provide a second signal on a second output, using the supply voltage and the control information. An output voltage between the first output and the second output, in a diagnostic mode of operation of the control circuit, can include a periodic signal having a peak-to-peak voltage greater than the supply voltage.

公开(公告)号：US09941894B1

公开(公告)日：2018-04-10

申请号：US15586848

申请日：2017-05-04

Applicant: Analog Devices Global

Inventor： Shurong Gu ,  Dennis A. Dempsey ,  GuangYang Qu ,  Hanqing Wang ,  Tony Yincai Liu

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/00 ,  G01N27/416 ,  G01N33/00

CPC classification number: G01N33/004 ,  G01N27/4163 ,  H03M1/002 ,  H03M1/662 ,  H03M1/68 ,  H03M1/765

Abstract: A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.

公开(公告)号：US09444487B1

公开(公告)日：2016-09-13

申请号：US14838097

申请日：2015-08-27

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H03M1/38 ,  H03M1/78 ,  H03M1/68

CPC classification number: H03M1/785 ,  H03M1/682 ,  H03M1/765

Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

Abstract translation: 在一个示例中，公开了一种多级数模转换器，包括：第一级具有第一组电路部件，第二级具有第二组电路部件，第三级具有第三组电路部件 第三级在第一和第二可转换的阻抗路径内提供负载; 其中所述DAC可在第一模式，第二模式和第三操作模式中的每一个中操作，其中在第一模式中，所述第一级可独立于所述第三级可切换地耦合到所述第二级; 在第二模式中，负载被耦合并呈现给电路部件的第二级的第一部分，并且在第三模式中，负载耦合并呈现给第二级电路部件的第二，不同部分。 还公开了相应的系统和方法。