公开(公告)号：US20170179969A1

公开(公告)日：2017-06-22

申请号：US15365867

申请日：2016-11-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Qingdong Meng ,  Hajime Shibata ,  Richard E. Schreier ,  Martin Steven McCormick ,  Yunzhi Dong ,  Jose Barreiro Silva ,  Jialin Zhao ,  Donald W. Paterson ,  Wenhua W. Yang

IPC: H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

公开(公告)号：US20150188562A1

公开(公告)日：2015-07-02

申请号：US14657919

申请日：2015-03-13

Applicant: ANALOG DEVICES GLOBAL

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M3/00 ,  H03M1/10

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行十进制化，进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。

公开(公告)号：US09768793B2

公开(公告)日：2017-09-19

申请号：US15365867

申请日：2016-11-30

Applicant: ANALOG DEVICES GLOBAL

Inventor： Qingdong Meng ,  Hajime Shibata ,  Richard E. Schreier ,  Martin Steven McCormick ,  Yunzhi Dong ,  Jose Barreiro Silva ,  Jialin Zhao ,  Donald W. Paterson ,  Wenhua W. Yang

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

公开(公告)号：US09209827B2

公开(公告)日：2015-12-08

申请号：US14657919

申请日：2015-03-13

Applicant: ANALOG DEVICES GLOBAL

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行十进制化，进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。

公开(公告)号：US10432210B1

公开(公告)日：2019-10-01

申请号：US16028002

申请日：2018-07-05

Applicant: Analog Devices Global Unlimited Company

Inventor： Shanthi Pavan Yendluri ,  Donald W. Paterson ,  Victor Kozlov ,  Hajime Shibata

IPC: H03M1/16 ,  H03M1/12 ,  H03M1/46 ,  H03M1/14

Abstract: Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.