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Patent Agency Ranking
公开(公告)号：US10367516B2
公开(公告)日：2019-07-30
申请号：US15674985
申请日：2017-08-11
Applicant: Analog Devices Global
Inventor： Frederick Carnegie Thompson , Varun Agrawal , Jose Barreiro Silva , Declan M. Dalton
IPC: H03L7/16 , H03M1/08 , H03K5/1252 , H03K7/06 , H03L7/089 , H03M1/06 , H03M1/12 , H04L27/06 , H03M1/74 , H03M3/00
Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.
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公开(公告)号：US20170179969A1
公开(公告)日：2017-06-22
申请号：US15365867
申请日：2016-11-30
Applicant: ANALOG DEVICES GLOBAL
Inventor： Qingdong Meng , Hajime Shibata , Richard E. Schreier , Martin Steven McCormick , Yunzhi Dong , Jose Barreiro Silva , Jialin Zhao , Donald W. Paterson , Wenhua W. Yang
Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.
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公开(公告)号：US20190052281A1
公开(公告)日：2019-02-14
申请号：US15674985
申请日：2017-08-11
Applicant: Analog Devices Global
Inventor： Frederick Carnegie Thompson , Varun Agrawal , Jose Barreiro Silva , Declan M. Dalton
CPC classification number: H03M1/0836 , H03K5/1252 , H03K7/06 , H03L7/08 , H03L7/0893 , H03L2207/50 , H03M1/0621 , H03M1/1245 , H03M1/747 , H03M3/43 , H03M3/458 , H04L27/066
Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.
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公开(公告)号：US09838031B2
公开(公告)日：2017-12-05
申请号：US15360984
申请日：2016-11-23
Applicant: Analog Devices Global
Inventor： Yunzhi Dong , Hajime Shibata , Trevor Clifford Caldwell , Zhao Li , Jialin Zhao , Jose Barreiro Silva
CPC classification number: H03M3/422 , H03M1/361 , H03M3/322 , H03M3/344 , H03M3/378 , H03M3/388 , H03M3/414 , H03M3/436 , H03M3/464
Abstract: For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.
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公开(公告)号：US09768793B2
公开(公告)日：2017-09-19
申请号：US15365867
申请日：2016-11-30
Applicant: ANALOG DEVICES GLOBAL
Inventor： Qingdong Meng , Hajime Shibata , Richard E. Schreier , Martin Steven McCormick , Yunzhi Dong , Jose Barreiro Silva , Jialin Zhao , Donald W. Paterson , Wenhua W. Yang
Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.
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