公开(公告)号：US20240264924A1

公开(公告)日：2024-08-08

申请号：US18106666

申请日：2023-02-07

Applicant: Arm Limited

Inventor： Michael BARTLING ,  Brendan James MORAN ,  Andreas Lars SANDBERG

IPC: G06F11/36

CPC classification number: G06F11/3612 ,  G06F11/3664

Abstract: A computer implemented method is provided. The computer implemented method includes receiving an intermediate representation of a source code, intentionally injecting a weak code path at a point within the intermediate representation to create a modified intermediate representation, performing a path profiling on the modified intermediate representation to generate a particular path identifier for each path within the modified intermediate representation, and identifying the particular path identifier of the weak code path for use by a monitoring system. A monitoring system is also provided. The monitoring system monitors an executable code during runtime for execution of a path having a particular path identifier corresponding to the injected intentionally weak code path.

公开(公告)号：US20210224201A1

公开(公告)日：2021-07-22

申请号：US16749006

申请日：2020-01-22

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Derek Del MILLER

IPC: G06F12/14

Abstract: An apparatus comprises memory storage circuitry comprising a plurality of memory storage locations to store data; an interface to receive an address from a requester; decryption circuitry to obtain a decrypted address by decrypting, based on a decryption key, an address received from the requester; and access control circuitry to select, based on the decrypted address obtained by the decryption circuitry, a memory storage location of the memory storage circuitry to be accessed.

公开(公告)号：US20200073819A1

公开(公告)日：2020-03-05

申请号：US16120637

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Geoffrey Wyman BLAKE ,  Prakash S. RAMRAKHYANI ,  Andreas Lars SANDBERG

IPC: G06F12/1009 ,  G06F12/0802

Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry. The translation determination comprises: calculating a higher level pointer to the intermediate level page table entry by applying a first predetermined function to the virtual address, calculating the intermediate level pointer by applying a second predetermined function to the virtual address, and initiating a memory access to retrieve in parallel the intermediate level pointer from the intermediate level page table entry and the translation from the last level page table entry.

公开(公告)号：US20240264801A1

公开(公告)日：2024-08-08

申请号：US18106274

申请日：2023-02-06

Applicant: Arm Limited

Inventor： Brendan James MORAN ,  Michael BARTLING ,  Andreas Lars SANDBERG

IPC: G06F7/501 ,  G06F5/01

CPC classification number: G06F7/501 ,  G06F5/01

Abstract: A 1-hot path signature accelerator includes a register, first and second accumulator, and an outer product circuit. The register stores an input frame, where the input frame has, at most, one bit of each element set. The first accumulator calculates a present summation by adding the input frame to a previous sum of previous input frames inputted to the 1-hot path signature accelerator within a timeframe. The outer product circuit receives each element of the present summation from the first accumulator and each element of the input frame stored in the register to output a present outer product. Since the input frame has at most one bit of each element set, the outer product circuit is reduced to a logical operation. The second accumulator outputs a present second-layer summation by adding the present outer product to a previous second-layer sum of outputs from the outer product circuit within the timeframe.

公开(公告)号：US20200264980A1

公开(公告)日：2020-08-20

申请号：US16865642

申请日：2020-05-04

Applicant: ARM Limited

Inventor： Wei WANG ,  Stephan DIESTELHORST ,  Wendy Arnott ELSASSER ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS

IPC: G06F12/0873 ,  G06F12/0868 ,  G06F12/126 ,  G06F11/14 ,  G11C5/14 ,  G06F12/02 ,  G06F12/0895 ,  G06F1/3206 ,  G06F12/0871

Abstract: An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.

公开(公告)号：US20190384501A1

公开(公告)日：2019-12-19

申请号：US16152485

申请日：2018-10-05

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG

IPC: G06F3/06

Abstract: An apparatus comprises control circuitry to control access to a memory implemented using a memory technology providing variable access latency. The control circuitry has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context. At least when the execution context switch meets a predetermined condition, a delay masking action is triggered to control subsequent memory access requests associated with the second execution context, for which the required data is already stored in the memory, to be serviced with a response delay which is independent of which addresses were accessed by the memory access requests associated with the first execution context. This can help guard against attacks which aim to exploit variation in response latency to gain insight into the addresses accessed by a victim execution context.

公开(公告)号：US20190155748A1

公开(公告)日：2019-05-23

申请号：US16181474

申请日：2018-11-06

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI

IPC: G06F12/1027

Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.

公开(公告)号：US20190155747A1

公开(公告)日：2019-05-23

申请号：US16169206

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI ,  Stephan DIESTELHORST

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/06 ,  G06F13/16 ,  G06F3/06

Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

公开(公告)号：US20230409487A1

公开(公告)日：2023-12-21

申请号：US17837108

申请日：2022-06-10

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG

IPC: G06F12/1045 ,  G06F12/0802

CPC classification number: G06F12/1045 ,  G06F2212/60 ,  G06F12/0802

Abstract: Partial-address-translation-invalidation request to cause cache control circuitry to: identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by a table address of a target page table entry when used as the branch page table entry; and trigger an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry. The given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of a corresponding region of address space corresponding to an output address specified by the target page table entry when used as the leaf page table entry.

公开(公告)号：US20230342150A1

公开(公告)日：2023-10-26

申请号：US18245840

申请日：2020-11-26

Applicant: Arm Limited

Inventor： Ilias VOUGIOUKAS ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30061 ,  G06F9/30036 ,  G06F9/3804

Abstract: Apparatuses and methods for branch prediction are provided. Branch prediction circuitry generates prediction with respect to branch instructions of whether those branches will be taken or not-taken. Hypervector generation circuitry assigns an arbitrary hypervector in deterministic dependence on an address of each branch instruction, wherein the hypervectors comprises at least 500 bits. Upon the resolution of a branch a corresponding hypervector is added to a stored taken hypervector or a stored not-taken hypervector in dependence on the resolution of the branch. The branch prediction circuitry generates a prediction for a branch instructions in dependence on a mathematical distance metric of a hypervector generated for that branch instruction from the stored taken hypervector or the not-taken hypervector.