公开(公告)号：US20240086202A1

公开(公告)日：2024-03-14

申请号：US17942554

申请日：2022-09-12

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU ,  Wei WANG

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3855 ,  G06F9/30145 ,  G06F9/32

Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

公开(公告)号：US20230325325A1

公开(公告)日：2023-10-12

申请号：US18044499

申请日：2021-08-16

Applicant: Arm Limited

Inventor： Wei WANG ,  Matthew James HORSNELL

IPC: G06F12/12 ,  G06F12/0897 ,  G06F12/0862

CPC classification number: G06F12/12 ,  G06F2212/601 ,  G06F12/0862 ,  G06F12/0897

Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.

公开(公告)号：US20200264980A1

公开(公告)日：2020-08-20

申请号：US16865642

申请日：2020-05-04

Applicant: ARM Limited

Inventor： Wei WANG ,  Stephan DIESTELHORST ,  Wendy Arnott ELSASSER ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS

IPC: G06F12/0873 ,  G06F12/0868 ,  G06F12/126 ,  G06F11/14 ,  G11C5/14 ,  G06F12/02 ,  G06F12/0895 ,  G06F1/3206 ,  G06F12/0871

Abstract: An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.

公开(公告)号：US20180286475A1

公开(公告)日：2018-10-04

申请号：US15886970

申请日：2018-02-02

Applicant: ARM Limited

Inventor： Wei WANG

IPC: G11C11/406

Abstract: An apparatus comprises first and second memory regions each to store data using a data storage technology for which retention of data for longer than a predetermined period of time is dependent on a refresh operation for refreshing data in the memory region being performed at a frequency that is greater than or equal to a minimum refresh frequency. The apparatus further comprises at least one controller to control storage of data in the first memory region with the refresh operation performed at a first frequency lower than said minimum refresh frequency when valid data is stored in the first memory region, and to control storage of data in the second memory region with the refresh operation performed at a second frequency that is greater than or equal to said minimum refresh frequency. The at least one controller is configured to communicate with the first memory region via a first memory channel and with the second memory region via a second memory channel.

公开(公告)号：US20230046064A1

公开(公告)日：2023-02-16

申请号：US17760190

申请日：2021-02-08

Applicant: ARM LIMITED ,  UNIVERSITY OF SOUTHAMPTON

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  Alexander Stewart WEDDELL ,  Matthew James WALKER ,  Wei WANG ,  James Edward MYERS

IPC: G06F1/3228 ,  G06F1/3296

Abstract: A computer-implemented method comprises generating computer executable code as one or more code portions; detecting a number of processing operations required to reach one or more predetermined stages in execution of each code portion; and associating with each code portion one or more progress indicators, each representing a respective execution stage of the one or more predetermined stages within execution of that code portion. The code portions are executed by a processor powered by an unpredictable power source. When the processor detects an energy condition indicating that no more than a reserve quantity of electrical energy is available, the progress indicators are used to determine whether or not to perform a checkpoint.

公开(公告)号：US20220114102A1

公开(公告)日：2022-04-14

申请号：US17069057

申请日：2020-10-13

Applicant: Arm Limited

Inventor： Wei WANG ,  Prakash S. RAMRAKHYANI ,  Gustavo Federico PETRI

IPC: G06F12/0875 ,  G06F12/0882 ,  G06F12/1009 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38 ,  G06F11/14 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a write buffer to buffer store requests issued by the processing circuitry, prior to the store data being written to at least one cache. Draining circuitry detects a draining trigger event having potential to cause loss of state stored in the at least one cache. In response to the draining trigger event, the draining circuitry performs a draining operation to identify whether the write buffer buffers any committed store requests requiring persistence, and when the write buffer buffers at least one committed store request requiring persistence, to cause the store data associated with the at least one committed store request to be written to persistent memory. This helps to eliminate barrier instructions from software, simplifying persistent programming and improving performance.

公开(公告)号：US20220004390A1

公开(公告)日：2022-01-06

申请号：US17593018

申请日：2019-11-26

Applicant: Arm Limited ,  THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： Vaibhav GOGTE ,  Wei WANG ,  Stephan DIESTELHORST ,  Peter M CHEN ,  Satish NARAYANAMY ,  Thomas Friedrich WENISCH

IPC: G06F9/38 ,  G06F9/52

Abstract: A data processing apparatus includes obtain circuitry that obtains a stream of instructions. The stream of instructions includes a barrier creation instruction and a barrier inhibition instruction. Track circuitry orders sending each instruction in the stream of instructions to processing circuitry based on one or more dependencies. The track circuitry is responsive to the barrier creation instruction to cause the one or more dependencies to include one or more barrier dependencies in which pre-barrier instructions, occurring before the barrier creation instruction in the stream, are sent before post-barrier instructions, occurring after the barrier creation instruction in the stream, are sent. The track circuitry is also responsive to the barrier inhibition instruction to relax the barrier dependencies to permit post-inhibition instructions, occurring after the barrier inhibition instruction in the stream, to be sent before the pre-barrier instructions.

公开(公告)号：US20200285479A1

公开(公告)日：2020-09-10

申请号：US16296507

申请日：2019-03-08

Applicant: Arm Limited ,  The Regents of The University of Michigan

Inventor： Vaibhav GOGTE ,  Wei WANG ,  Stephan DIESTELHORST ,  Peter M. CHEN ,  Satish NARAYANASAMY ,  Thomas Friedrich WENISCH

IPC: G06F9/38 ,  G06F9/52

Abstract: A data processing apparatus includes obtain circuitry that obtains a stream of instructions. The stream of instructions includes a barrier creation instruction and a barrier inhibition instruction. Track circuitry orders sending each instruction in the stream of instructions to processing circuitry based on one or more dependencies. The track circuitry is responsive to the barrier creation instruction to cause the one or more dependencies to include one or more barrier dependencies in which pre-barrier instructions, occurring before the barrier creation instruction in the stream, are sent before post-barrier instructions, occurring after the barrier creation instruction in the stream, are sent. The track circuitry is also responsive to the barrier inhibition instruction to relax the barrier dependencies to permit post-inhibition instructions, occurring after the barrier inhibition instruction in the stream, to be sent before the pre-barrier instructions.

公开(公告)号：US20190324908A1

公开(公告)日：2019-10-24

申请号：US15960927

申请日：2018-04-24

Applicant: Arm Limited

Inventor： Stephan DIESTELHORST ,  Wei WANG

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F9/46 ,  G06F9/4401

Abstract: Methods and apparatus are provided for executing a transaction in a data processing system, responsive to each memory access of the transaction, a transaction log is updated in a persistent memory. After execution of the transaction and when the transaction log is complete, the transaction log is marked as ‘pending’. When all values modified in the transaction have been written back to the persistent memory, the transaction log is marked as ‘free’. When, following a reboot, a transaction log is marked as ‘pending’, data stored in the transaction log is copied to the persistent memory at addresses indicated in the transaction log. After the copying is complete, the transaction log is marked as ‘free’. Cache values modified in the transaction may be written back to persistent memory when evicted, and values read in the transaction may be read from the cache rather than from the transaction log.