公开(公告)号：US20170228493A1

公开(公告)日：2017-08-10

申请号：US15498804

申请日：2017-04-27

Applicant: ARM Limited

Inventor： Gregory Munson YERIC

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F7/70383 ,  G03F7/70433 ,  G06F2217/12 ,  H01L21/027 ,  H01L22/14 ,  H01L22/20

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

公开(公告)号：US20160161550A1

公开(公告)日：2016-06-09

申请号：US14560755

申请日：2014-12-04

Applicant: ARM Limited

Inventor： Gregory Munson YERIC ,  Vikas CHANDRA

IPC: G01R31/28 ,  H01L25/065 ,  H01L21/66

CPC classification number: G01R31/2855 ,  G01R31/2856 ,  H01L22/30 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

Abstract translation: 集成电路装置具有至少一个环境硬化的模具和至少一个较少环境硬化的模具。 环境硬化的模具上的环境硬化电路在暴露于预定的环境条件下比在环境硬化的模具上的环境硬化较差的电路更能抵抗劣化。 骰子使用3D或2.5D集成电路技术进行组合。 这对于在不利的环境条件（例如高温）下的测试电路或在这种情况下提供电路进行操作非常有用。

公开(公告)号：US20150026650A1

公开(公告)日：2015-01-22

申请号：US13944129

申请日：2013-07-17

Applicant: ARM LIMITED

Inventor： Gregory Munson YERIC

IPC: G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G03F7/70383 ,  G03F7/70433 ,  G06F2217/12 ,  H01L21/027 ,  H01L22/14 ,  H01L22/20

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

Abstract translation: 使用直接写入光刻步骤制造集成电路，以至少部分地形成集成电路内的至少一个层。 测量至少部分形成的集成电路的性能特征，然后根据这些性能特性来改变要应用直写式光刻步骤的布局设计。 因此，可以改变单个集成电路，集成电路晶片或一批晶片的性能。